Modified Level Restorers Using Current Sink and Current Source Inverter Structures for BBL-PT Full Adder

Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process

Power-efficient design of 16-bit mixed-operand multipliers

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 53).Multiplication is an expensive and slow arithmetic operation, which plays an important role in many DSP algorithms. It usually lies in the critical-delay paths, having an effect on performance of the system as well as consuming large power. Consequently, significant improvements in both power and performance can be achieved in the overall DSP system by carefully designing and optimizing power and performance of the multiplier. This thesis explores several circuit-level techniques for power-efficiently designing multipliers, including supply voltage reduction, efficient multiplication algorithms, low power circuit logic styles, and transistor sizing using dynamic and static tuners. Based on these techniques, several 16-bit multipliers have been successfully designed and implemented in 0.13[micro]m CMOS technology at the supply voltage of 1.5V and 0.9V. The multipliers are modified to handle multiplications of two 16-bit operands in which each can be either signed magnitude or two's complement formats. Examining power-performance characteristics of these multipliers reveals that both array and tree structures are feasible solutions for designing 16-bit multipliers, and complementary CMOS and single-ended CPL-TG logics are promising candidates for power-efficient design. The appropriate choices of structures and logic styles depend on power and performance constraints of the particular design.by Sataporn Pornpromlikit.M.Eng

Low Power Thermometer code to Binary code Encoder based Flash ADC

Architectural level design of a low power Thermometer code to Binary code Encoder for a Flash ADC of 4 bit resolution is presented. In the proposed architecture the thermometer code is initially converted into intermediate gray code using 2:1 multiplexers and then to the binary code using XOR gates. Various logic styles (CMOS, Transmission gate logic, DPL, CPL, EEPL, LEAP, SRPL, PPL) are studied for the design of 2:1 Multiplexers and XOR gate. The performance of proposed architecture is compared with other available architectures like multiplexer based direct conversion method, wallace tree encoder, intermediate gray code based encoder using basic gates and using 2:1 multiplexers. From the study it is obtained that the proposed architecture consumes lesser power and gives a comparable delay performance (only direct conversion using 2:1 multiplexers gives better delay performance). The proposed architecture uses minimum number of multiplexers for the conversion and consumes 25.64µW of power with a power supply of 1.8V. A 4 bit flash ADC is designed using the proposed encoder in Cadence UMC 0.18µm technology and the working is verified

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

Extended-Range Second-Order Incremental Sigma-Delta ADC

A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion).A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion)

A full-custom digital-signal-processing unit for real-time cortical blood flow monitoring

Master'sMASTER OF ENGINEERIN

Direct Digital Frequency Synthesizer Architecture for Wireless Communication in 90 NM CMOS Technology

Software radio is one promising field that can meet the demands for low cost, low power, and high speed electronic devices for wireless communication. At the heart of software radio is a programmable oscillator called a Direct Digital Synthesizer (DDS). DDS has the capabilities of rapid frequency hopping by digital software control while operating at very high frequencies and having sub-hertz resolution. Nevertheless, the digital-to-analog converter (DAC) and the read-only-memory (ROM) look-up table, building blocks of the DDS, prevent the DDS to be used in wireless communication because they introduce errors and noises to the DDS and their performances deteriorate at high speed. The DAC and ROM are replaced in this thesis by analog active filters that convert the square wave output of the phase accumulator directly into a sine wave. The proposed architecture operates with a reference clock of 9.09 GHz and can be fully-integrated in 90 nm CMOS technology