Development, fabrication, and characterization of a vertical-diffused MOS process for power RF applications

High power radio frequency (RF) applications have become important because of a growing demand from the wireless market. With their superior switching speed, power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become one of the well-known technologies used in high power RF systems. The primary focus of this thesis work was the development, fabrication, and characterization of discrete Verticaldrain lateral-Diffused MOS (VDMOS) power transistors using an interdigitated source/gate design. Several types of high power devices were also presented for comparison to the VDMOS structure. This thesis describes the overall purpose and the objectives of the proposed project, and provides the methodology used to complete these objectives. This project supports a new development initiative of the project sponsor, Spectrum Devices, Inc., who has been working with RIT in power bipolar technologies over the last two years. The process steps to create a 50 V power VDMOS transistor structure were designed using Silvaco ATHENA (SUPREM-IV) process simulation. Typical power VDMOS transistor fabrication steps were used as a starting point with modifications to include Faraday and UIS implant steps to address certain parasitic effects. The Faraday shield implant was performed to shift the parasitic gate- field capacitance over to the input side of the device, which should dramatically improve the frequency response of the device. The UIS implant was used to reduce the parasitic BJT of a power VDMOS transistor. The implementation of the proposed structure also eliminated the need for an added masking operation for each implant step, and kept the structure self- aligned to the gate stack. This eliminated potential overlay tolerances and error that may be encountered in photolithography steps. The initial process parameters were carefully varied and adjusted to meet the target specifications (such as threshold voltage, breakdown voltage, gate oxide thickness, etc.) using ATHENA and ATLAS simulation software. After the device fabrication was completed, DC testing was performed on the fabricated VDMOS transistors both at RIT and at Spectrum Devices. A successful extraction of the transfer curves, family of curves, and breakdown voltage plots both in low and high current settings was achieved. The designed process produced a power VDMOS with a breakdown voltage of up to 180 V, a threshold voltage of ~3.8 V, a transconductance up to ~7 mhos, and an operating current of nearly 5 A. The experimental results were compared to the target specification provided by Spectrum Devices. In addition, impacts of the Faraday shield implant on the breakdown voltage and terminal capacitances of a VDMOS device were verified through DC testing. Preliminary wafer- level AC testing was performed and demonstrated the functional performance of the device up to 100 kHz frequency range. Although it would be interesting to see the impact of UIS implant step on a device performance, no AC test was yet to be performed. This work presented the first power VDMOS transistors successfully fabricated and characterized at RIT. With the data and information obtained from this thesis project, process modifications and adjustments should yield devices with improved performance

An Integrated BiCMOS driver chip for medium power applications

The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies. The custom integrated circuit includes four outputs each capable of switching over 500 mA at 30 volts, at a frequency of up to 1 MHz. The development effort includes the design of the chip with its component circuits and cells. Standard cell CMOS logic gates along with drive and interface circuits were designed and characterized. An appropriate BiCMOS process was developed which utilizes an n-well based 4-micron polysilicon gate MOS technology and vertical NPNs with subcollector and double emitter implants. The chip performance specifications are evaluated with respect to technology requirements and device characteristics, and trade-offs in the design of the chip and the process are examined. Process and device modeling results are compared with the measured data, which show that the objectives of the design are successfully met for the various applications involving resistive, capacitive, and inductive loads

High Performance Low Voltage Power Mosfet For High-frequency Synchronous Buck Converters

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed

Design and fabrication of lateral high power devices for power integrated circuits applications

The incorporation of high power devices on the same chip as that of the circuitry controlling the high power device has been shown to provide several major advantages over discrete and multichip module designs. The major focus of this work is the development of lateral high power devices that are compatible with R.I.T.\u27s low power CMOS process. The thrust of this study is to evaluate the feasibility of fabricating Power Integrated Circuits at R.I.T\u27s semiconductor die manufacturing laboratory. As part of the development, several types of high power devices were investigated and the Power MOSFET and IGBT were chosen to be fabricated. The Power MOSFET and IGBT were chosen because they were the least complicated and would provide the greatest probability of functionality. The bulk of the work involved studying the effect of the field plate overlap on the breakdown voltage and the on state resistance. The basic process needed to fabricate the power device was designed and a SUPREM 4 simulation has been generated. The designed process produced a power MOSFET with a breakdown voltage of 50 volts and an operating current of nearly 0.5 amps with an on state resistance of 35Q, while maintaining the standard CMOS operating characteristics for the low power devices. The results are discussed and recommendation for future work at R.I.T. are provided

Simulation of superjunction MOSFET devices

Master'sMASTER OF ENGINEERIN

Optimization of power MOSFET devices suitable for integrated circuits

Táto doktorská práca sa zaoberá návrhom laterálnych výkonových tranzistorov s nízkym špecifickým odporom pri zapnutom stave, vhodných pre integráciu do Integrovaných Obvodov.This doctoral thesis deals with the design of lateral power transistor with lower specific on-resistance for integration into IC.The new model of MOSFET with waffle gate pattern is there described. For first, time the conformal transformation the Schwarz-Christoffel mapping has been used for the description of nonhomogeneous current distribution in the channel area of MOSFET with waffle gate pattern. In addition base on the figure of merit definition Area Increment (AI) the topological theoretical limit of MOSFET with waffle gate pattern has been a first time defined

Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies

Electrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be destroyed easily, so ESD protection solutions are essential to semiconductor industry. ESD protection design consists of on-chip and off-chip ESD protection design, and the research works in this dissertation are all conducted in on-chip level, which incorporate the ESD protection devices and circuits into the microchip, to provide with basic ESD protection from manufacturing to customer use. The basic idea of ESD protection design is to provide a path with low impedance which directs most of the ESD current to flow through itself instead of the core circuit, and the ESD protection path must be robust enough to make sure that it does not fail before the core circuit. In this way, proper design on protection devices and circuits should be considered carefully. To assist the understanding and design of ESD protection, the ESD event in real world has been classified into a few ESD model including Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM), etc. Some mainstream testing method and industry standard are also introduced, including Transmission Line Pulse (TLP), and IEC 61000-4-2. ESD protection devices including diode, Gate-Grounded N-type MOSFET (GGNMOS), Silicon Controlled Rectifier (SCR) are basic elements for ESD protection design. In this dissertation, the device characteristics in ESD event and their applications are introduced. From the perspective of the whole chip ESD protection design, the concept of circuit level ESD protection and the ESD clamps are also briefly introduced. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation is widely used in ESD protection design. In this dissertation, TCAD and SPICE simulation are carried out for a few times for both of pre-tapeout evaluation on characteristics of the proposed device and circuit and post-tapeout analysis on structure operating mechanism. Automotive electronics has been a popular subject in semiconductor industry, and due to the special requirement of the automotive applications like the capacitive pins, the ESD protection device used in such applications need to be specially designed. In this dissertation, a few SCRs without snapback are discussed in detail. To avoid core circuit damages caused the displacement current induced by the large snapback in conventional SCR, an eliminated/minimized snapback is preferred in a selection of the protection device. Two novel SCRs are proposed for High Voltage (HV), Medium Voltage (MV), and Low Voltage (LV) automotive ESD protection. The typical operating temperature for ICs is up to 125°C, however in automotive applications, the operating temperature may extend up to 850°C. In this way, the characteristics of the ESD protection device under the elevated temperatures will be an essential part to investigate for automotive ESD protection design. In this dissertation, the high temperature characteristics of ESD protection devices including diode and a few SCRs is measured and discussed in detail. TCAD simulation are also conducted to explain the underlying physical mechanism. This work provides with a useful insight and information to ESD protection design in high temperature applications. Besides the high temperature environment, ESD protection are also highly needed for electronics working in other extreme environment like the space. Space is an environment that contains kinds of radiation source and at the same time can generate abundant ESD. The ESD adhering to the space systems could be a potential threat to the space electronics. At the same time, the characteristics of the ESD protection part especially the basic protection device used in the space electronics could be influenced after the irradiation in the space. Therefore, the investigation of the radiation effects on ESD protection devices are necessary. In this dissertation, the total ionizing dose (TID) effects on ESD protection devices are investigated. The devices are irradiated with 1.5 MeV He+ and characterized with TLP tester. The pre- and post-irradiation characteristics are compared and the variation on key ESD parameters are analyzed and discussed. This work offers a useful insight on ESD devices\u27 operation under TID and help with the device designing on ESD protection devices for space electronics. Single ESD protection devices are essential part constructing the ESD protection network, however the optimization on ESD clamp circuit design is also important on building an efficient whole chip ESD protection network. In this dissertation, the design and simulation of a novel voltage triggered ESD detection circuit are introduced. The voltage triggered ESD detection circuit is proposed in a 0.18 um CMOS technology. Comparing with the conventional RC based detection circuit, the proposed circuit realizes a higher triggering efficiency with a much smaller footprint, and is immune to false triggering under fast power-up events. The proposed circuit has a better sensitivity to ESD event and is more reliable in ESD protection applications. The leakage current has been a concern with the scaling down of the thickness of the gate oxide. Therefore, a proper design of the ESD clamp for power rail ESD protection need to be specially considered. In this dissertation, a design of a novel ESD clamp with low leakage current is analyzed. The proposed clamp realized a pretty low leakage current up to 12 nA, and has a smaller footprint than conventional design. It also has a long hold-on time under ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the operation of the proposed ESD clamp

Journal of Microelectronic Research - May 2003

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