High-speed simulation of PCB emission and immunity with frequency-domain IC/LSI source models

Some recent results from research conducted in the EMC group at Okayama University are reviewed. A scheme for power-bus modeling with an analytical method is introduced. A linear macro-model for ICs/LSIs, called the LECCS model, has been developed for EMI and EMS simulation. This model has a very simple structure and is sufficiently accurate. Combining the LECCS model with analytical simulation techniques for power-bus resonance simulation provides a method for high-speed EMI simulation and decoupling evaluation related to PCB and LSI design. A useful explanation of the common-mode excitation mechanism, which utilizes the imbalance factor of a transmission line, is also presented. Some of the results were investigated by implementing prototypes of a high-speed EMI simulator, HISES. </p

A Time Domain Approach to Power Integrity for Printed Circuit Boards

Power integrity is becoming increasingly relevant due to increases in device functionality and switching speeds along with reduced operating voltage. Large current spikes at the device terminals result in electromagnetic disturbances which can establish resonant patterns affecting the operation of the whole system. These effects have been examined using a finite difference time domain approach to solve Maxwell's equations for the PCB power and ground plane configuration. The simulation domain is terminated with a uniaxial perfectly matched layer to prevent unwanted reflections. This approach calculates the field values as a function of position and time and allows the evolution of the field to be visualized. The propagation of a pulse over the ground plane was observed demonstrating the establishment of a complex interference pattern between source and reflected wave fronts and then between multiply reflected wave fronts. This interference which affects the whole ground plane area could adversely affect the operation of any device on the board. These resonant waves persist for a significant time after the initial pulse. Examining the FFT of the ground plane electric field response showed numerous resonant peaks at frequencies consistent with the expected values assuming the PCB can be modelled as a resonant cavity with two electric and four magnetic field boundaries.Comment: Presented at The University of Bolton Research and Innovation Conference, Bolton, UK. 16th September, 201

Modeling of gapped power bus structures for isolation using cavity modes

Power bus resonance characteristics of a gapped power-plane with a slit and a split power-plane with a gap were studied, using a fast algorithm based on a full cavity-mode resonator model and the segmentation method. Inductance and capacitance models were used to account for a field coupling along the slit and across the gap, respectively. Good agreements between the calculated and measured results were found to demonstrate the effectiveness and accuracy of our fast algorithm and the segmentation method, as well as the inductance model for the slit and the capacitance model for the gap. </p

Quantifying SMT Decoupling Capacitor Placement in dc Power-Bus Design for Multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach

Electromagnetic Interference (EMI) of System-on-Package (SOP)

Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration

Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques

A higher performance of computing systems is being demanded year after year, driving the digital industry to fiercely compete for offering the fastest computer system at the lowest cost. In addition, as computing system performance is growing, power delivery networks (PDN) and power integrity (PI) designs are getting increasingly more relevance due to the faster speeds and more parallelism required to obtain the required performance growth. The largest data throughput at the lowest power consumption is a common goal for most of the commercial computing systems. As a consequence of this performance growth and power delivery tradeoffs, the complexity involved in analyzing and designing PDN in digital systems is being increased. This complexity drives longer design cycle times when using traditional design tools. For this reason, the need of using more efficient design methods is getting more relevance in order to keep designing and launching products in a faster manner to the market. This trend pushes PDN designers to look for methodologies to simplify analysis and reduce design cycle times. The main objective for this Master’s thesis is to propose alternative methods by exploiting reliable simulation approaches and efficient numerical optimization techniques to analyze and design PDN to ensure power integrity. This thesis explores the use of circuital models and electromagnetic (EM) field solvers in combination with numerical optimization methods, including parameter extraction (PE) formulations. It also establishes a sound basis for using space mapping (SM) methodologies in future developments, in a way that we exploit the advantages of the most accurate and powerful models, such as 3D full-wave EM simulators, but conserving the simplicity and low computational resourcing of the analytical, circuital, and empirical models

Modeling and optimal design of shorting vias to suppress radiated emission in high-speed alternating PCB planes

An analytical mode analysis of vias in the multilayered printed-circuit-board periphery is developed to suppress the electromagnetic radiation induced by ground bounce. After separating the even and odd modes in alternating planes, the far-field radiation of parallel plates is derived using Huygens' principle. It is mainly contributed by the odd mode excitation, while the even mode sets a lower bound on the radiation level from the system when shorting vias are inserted between alternating ground plates. For the odd-mode radiation, a canonical problem is then constructed and analytically solved by applying image theory. Based on that, a systematic approach to achieve the optimum suppression design is developed for the various geometry parameters of the shorting vias, including the pitch, radius, and distance to the board edge. Full-wave simulation and measurement are also presented and the good agreement with the theoretical prediction validates the correctness and efficiency of the present analysis and design

Via transition modeling and charge replenishment of the power delivery network in multilayer PCBs

In the first article of this thesis, the charge delivery in the power distribution network for printed circuit board has been analyzed in the time-domain. Performing all the simulations and analyzing the PDN physics and modeling, I contributed to a better understanding of the time-domain decoupling mechanism. The second paper studies the noise coupling sing a segmentation approach combined with a via-to-antipad capacitance model and a plane-pair cavity model. Building equivalent circuit models as well as analyzing design strategies, I contributed to a new approach for the PDN analysis in multilayer PCBs. The third article discusses how to estimate the amount of current needed for large ICs and how to evaluate the amount of noise voltage due to this current draw. After accurate discussion of the design strategies, I modeled and simulated the free evolution of a charged PCB with and without decoupling capacitors. The depletion of charges stored between the power buses in time and frequency-domain has been investigated as a function of the plane thickness, SMT decoupling closeness in the fourth paper. With my contribution, the time and frequency-domain in the PDN have been related using circuit approach. In the fifth paper, I analyzed a 26-layer printed circuit board performing milling, measurements and building circuit models. It is the first time that the segmentation approach has been used for differential geometry. In addition, Debye materials have been implemented in the cavity model --Abstract, page iv

Estimating the Power Bus Impedance of Printed Circuit Boards with Embedded Capacitance

Embedded capacitance is an alternative to discrete decoupling capacitors and is achieved by enhancing the natural capacitance between closely spaced power and return planes. This paper employs a simple cavity model to investigate the features affecting the power bus impedance of printed circuit boards with embedded capacitance