Interfacing of neuromorphic vision, auditory and olfactory sensors with digital neuromorphic circuits

The conventional Von Neumann architecture imposes strict constraints on the development of intelligent adaptive systems. The requirements of substantial computing power to process and analyse complex data make such an approach impractical to be used in implementing smart systems. Neuromorphic engineering has produced promising results in applications such as electronic sensing, networking architectures and complex data processing. This interdisciplinary field takes inspiration from neurobiological architecture and emulates these characteristics using analogue Very Large Scale Integration (VLSI). The unconventional approach of exploiting the non-linear current characteristics of transistors has aided in the development of low-power adaptive systems that can be implemented in intelligent systems. The neuromorphic approach is widely applied in electronic sensing, particularly in vision, auditory, tactile and olfactory sensors. While conventional sensors generate a huge amount of redundant output data, neuromorphic sensors implement the biological concept of spike-based output to generate sparse output data that corresponds to a certain sensing event. The operation principle applied in these sensors supports reduced power consumption with operating efficiency comparable to conventional sensors. Although neuromorphic sensors such as Dynamic Vision Sensor (DVS), Dynamic and Active pixel Vision Sensor (DAVIS) and AEREAR2 are steadily expanding their scope of application in real-world systems, the lack of spike-based data processing algorithms and complex interfacing methods restricts its applications in low-cost standalone autonomous systems. This research addresses the issue of interfacing between neuromorphic sensors and digital neuromorphic circuits. Current interfacing methods of these sensors are dependent on computers for output data processing. This approach restricts the portability of these sensors, limits their application in a standalone system and increases the overall cost of such systems. The proposed methodology simplifies the interfacing of these sensors with digital neuromorphic processors by utilizing AER communication protocols and neuromorphic hardware developed under the Convolution AER Vision Architecture for Real-time (CAVIAR) project. The proposed interface is simulated using a JAVA model that emulates a typical spikebased output of a neuromorphic sensor, in this case an olfactory sensor, and functions that process this data based on supervised learning. The successful implementation of this simulation suggests that the methodology is a practical solution and can be implemented in hardware. The JAVA simulation is compared to a similar model developed in Nengo, a standard large-scale neural simulation tool. The successful completion of this research contributes towards expanding the scope of application of neuromorphic sensors in standalone intelligent systems. The easy interfacing method proposed in this thesis promotes the portability of these sensors by eliminating the dependency on computers for output data processing. The inclusion of neuromorphic Field Programmable Gate Array (FPGA) board allows reconfiguration and deployment of learning algorithms to implement adaptable systems. These low-power systems can be widely applied in biosecurity and environmental monitoring. With this thesis, we suggest directions for future research in neuromorphic standalone systems based on neuromorphic olfaction

FPGA TO POWER SYSTEM THEORIZATION FOR A FAULT LOCATION AND SPECIFICATION ALGORITHM

Fault detection and location algorithms have allowed for the power industry to alter the power grid from the traditional model to becoming a smart grid. This thesis implements an already established algorithm for detecting faults, as well as an impedance-based algorithm for detecting where on the line the fault has occurred and develops a smart algorithm for future HDL conversion using Simulink. Using the algorithms, the ways in which this implementation can be used to create a smarter grid are the fundamental basis for this research. Simulink was used to create a two-bus power system, create environment variables, and then Matlab was used to program the algorithm such that it could be FPGA-implementable, where the ways in which one can retrieve the data from a power line has been theorized. This novel approach to creating a smarter grid was theorized and created such that real-world applications may be further implemented in the future

A Review of Fault Diagnosing Methods in Power Transmission Systems

Transient stability is important in power systems. Disturbances like faults need to be segregated to restore transient stability. A comprehensive review of fault diagnosing methods in the power transmission system is presented in this paper. Typically, voltage and current samples are deployed for analysis. Three tasks/topics; fault detection, classification, and location are presented separately to convey a more logical and comprehensive understanding of the concepts. Feature extractions, transformations with dimensionality reduction methods are discussed. Fault classification and location techniques largely use artificial intelligence (AI) and signal processing methods. After the discussion of overall methods and concepts, advancements and future aspects are discussed. Generalized strengths and weaknesses of different AI and machine learning-based algorithms are assessed. A comparison of different fault detection, classification, and location methods is also presented considering features, inputs, complexity, system used and results. This paper may serve as a guideline for the researchers to understand different methods and techniques in this field

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly. Therefore, proposed a novel particle swarm based ADPLL (PS-ADPLL) with Coordinate Rotation Digital Computer (CORDIC) algorithm to attain the lock state of the ADPLL for the low-frequency applications. In the proposed architecture, the D flip-flop matches the frequency and the phase of the output and reference pulses and produces an error signals up and down signal. The up/down counter removes the higher frequency part and produces a carry and the borrow signal. These carry and borrow signals are then fed into the increment decrement counters to produce the output signal matching the frequency of the reference signal. However, the time delay is increased for low-frequency applications, which is critical for the lock state. So, the delay line length is calculated by the CORDIC algorithm and is optimized by the particle swarm activated in the phase detector to match the output pulse with the reference pulse and make ADPLL into a locked state. The presented PS-ADPLL is tested in FPGA. Furthermore, the performance parameters are evaluated and compared with other current techniques to calculate the improvement score

Decoding of Decode and Forward (DF) Relay Protocol using Min-Sum Based Low Density Parity Check (LDPC) System

Decoding high complexity is a major issue to design a decode and forward (DF) relay protocol. Thus, the establishment of low complexity decoding system would beneficial to assist decode and forward relay protocol. This paper reviews existing methods for the min-sum based LDPC decoding system as the low complexity decoding system. Reference lists of chosen articles were further reviewed for associated publications. This paper introduces comprehensive system model representing and describing the methods developed for LDPC based for DF relay protocol. It is consists of a number of components: (1) encoder and modulation at the source node, (2) demodulation, decoding, encoding and modulation at relay node, and (3) demodulation and decoding at the destination node. This paper also proposes a new taxonomy for min-sum based LDPC decoding techniques, highlights some of the most important components such as data used, result performances and profiles the Variable and Check Node (VCN) operation methods that have the potential to be used in DF relay protocol. Min-sum based LDPC decoding methods have the potential to provide an objective measure the best tradeoff between low complexities decoding process and the decoding error performance, and emerge as a cost-effective solution for practical application

Intelligent Omni-Surfaces for Full-Dimensional Wireless Communications: Principle, Technology, and Implementation

The recent development of metasurfaces has motivated their potential use for improving the performance of wireless communication networks by manipulating the propagation environment through nearly-passive sub-wavelength scattering elements arranged on a surface. However, most studies of this technology focus on reflective metasurfaces, i.e., the surface reflects the incident signals towards receivers located on the same side of the transmitter, which restricts the coverage to one side of the surface. In this article, we introduce the concept of intelligent omni-surface (IOS), which is able to serve mobile users on both sides of the surface to achieve full-dimensional communications by jointly engineering its reflective and refractive properties. The working principle of the IOS is introduced and a novel hybrid beamforming scheme is proposed for IOS-based wireless communications. Moreover, we present a prototype of IOS-based wireless communications and report experimental results. Furthermore, potential applications of the IOS to wireless communications together with relevant research challenges are discussed

Power allocation and linear precoding for wireless communications with finite-alphabet inputs

This dissertation proposes a new approach to maximizing data rate/throughput of practical communication system/networks through linear precoding and power allocation. First, the mutual information or capacity region is derived for finite-alphabet inputs such as phase-shift keying (PSK), pulse-amplitude modulation (PAM), and quadrature amplitude modulation (QAM) signals. This approach, without the commonly used Gaussian input assumptions, complicates the mutual information analysis and precoder design but improves performance when the designed precoders are applied to practical systems and networks. Second, several numerical optimization methods are developed for multiple-input multiple-output (MIMO) multiple access channels, dual-hop relay networks, and point-to-point MIMO systems. In MIMO multiple access channels, an iterative weighted sum rate maximization algorithm is proposed which utilizes an alternating optimization strategy and gradient descent update. In dual-hop relay networks, the structure of the optimal precoder is exploited to develop a two-step iterative algorithm based on convex optimization and optimization on the Stiefel manifold. The proposed algorithm is insensitive to initial point selection and able to achieve a near global optimal precoder solution. The gradient descent method is also used to obtain the optimal power allocation scheme which maximizes the mutual information between the source node and destination node in dual-hop relay networks. For point-to-point MIMO systems, a low complexity precoding design method is proposed, which maximizes the lower bound of the mutual information with discretized power allocation vector in a non-iterative fashion, thus reducing complexity. Finally, performances of the proposed power allocation and linear precoding schemes are evaluated in terms of both mutual information and bit error rate (BER). Numerical results show that at the same target mutual information or sum rate, the proposed approaches achieve 3-10dB gains compared to the existing methods in the medium signal-to-noise ratio region. Such significant gains are also indicated in the coded BER systems --Abstract, page iv-v

A Real-Time Smart Sensor for High-Resolution Frequency Estimation in Power Systems

Power quality monitoring is a theme in vogue and accurate frequency measurement of the power line is a major issue. This problem is particularly relevant for power generating systems since the generated signal must comply with restrictive standards. The novelty of this work is the development of a smart sensor for real-time high-resolution frequency measurement in accordance with international standards for power quality monitoring. The proposed smart sensor utilizes commercially available current clamp, hall-effect sensor or resistor as primary sensor. The signal processing is carried out through the chirp z-transform. Simulations and experimental results show the efficiency of the proposed smart sensor

A new readout control system for the LHCb upgrade at CERN

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and a first hardware implementation of a new fast Readout Control system for the LHCb upgrade, which will be entirely based on FPGAs and bi-directional links. We also outline the real-time implementations of the new Readout Control system, together with solutions on how to handle the synchronous distribution of timing and synchronous information to the complex upgraded LHCb readout architecture. One section will also be dedicated to the control and usage of the newly developed CERN GBT chipset to transmit fast and slow control commands to the upgraded LHCb Front-End electronics. At the end, we outline the plans for the deployment of the system in the global LHCb upgrade readout architecture