Crosstalk minimization of local channel routing algorithms in VLSI CAD

The greedy and left edge algorithms, as applied to local routing in VLSI CAD, were modified to decrease crosstalk between neighboring wires. The modifications on the algorithms use spacing, and segregation to improve the routing of wires in a channel. The modified greedy and left edge algorithms use a grid, but the minimum distance between two wires can be varied depending on the crosstalk between them. Crosstalk information must be obtained separately and is part of the required set of inputs to the algorithms. The improved algorithms route all the channel problems tested in less tracks than the original algorithms, if crosstalk constraints exist, and in the same number of tracks, if no crosstalk constraints exist

Using ant colony optimization for routing in microprocesors

Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers

Technologies for single chip integrated optical gyroscopes

Optical gyroscopes are being employed for navigational purposes for decades now and have achieved comparable or better reliability and performance than rotor-based gyroscopes. Mechanical gyros are however generally bulky, heavy and consume more power which make them unsuitable for miniaturized applications such as cube satellites and drones etc. Therefore, much effort is being expended worldwide to fabricate optical gyros having tactical grade robustness and reliability, small size, weight, cost and power consumption with minimal sacrifice of sensitivity. Integrated optics is an obvious approach to achieving this. This work comprises detailed comparative analysis of different types and structures of integrated optical gyroscopes to find out the suitable option for applications which require a resolution of <10 o/h. Based on the numerical analysis, Add-drop ring resonator-based gyro is found to be a suitable structure for integration which has a predicted shot noise limited resolution of 27 o/h and 2.71 o/h for propagation losses of 0.1 dB/cm and 0.01 dB/cm respectively. An integrated gyro is composed of several optical components which include a laser, 3dB couplers, phase/frequency modulators, sensing cavity and photodetectors. This requires hybrid integration of multiple materials technologies and so choices about which component should be implemented in which technology. This project also undertakes theoretical optimization of few of the above-mentioned optical components in materials systems that might offer the most convenient/tolerant option, this including 3dB coupler, thermo-optic phase modulator and sensing cavity (resonator and waveguide loop). In particular, the sensing element requires very low propagation loss waveguides which can best be realised from Si3N4 or Ta2O5. The optimised Si3N4 or Ta2O5 waveguides however are not optimal for other functions and this is shown and alternatives explored where the Si3N4 or Ta2O5 can easily be co-integrated. The fabrication process of low loss Si3N4 and Ta2O5 waveguides are also reported in this thesis. Si3N4 films were grown by using low pressure chemical vapor deposition (LPCVD) technique. Dry etching of Si3N4 films have been optimized to produce smooth and vertical sidewalls. Experimental results predicted that the propagation loss of 0.009 dB/cm is achievable by using optimum waveguide dimensions and silica cladding with the relatively standard processes available within the Laser Physics Centre at the Australian National University. A CMOS back end of line compatible method was developed to deposit good quality Ta2O5 films and silica claddings through ion beam sputtering (IBS) method. Plasma etching of Ta2O5 waveguides has been demonstrated by using a gas combination of CHF3/SF6/Ar/O2. Oxygen was introduced into the chamber to produce non-vertical sidewalls, so the waveguides could be cladded without voids with IBS silica. Average propagation losses of 0.17 dB/cm were achieved from Ta2O5 waveguides which appeared after extensive investigation to be limited by the spatial inhomogeneity of the processing. Lastly, a detailed theoretical and experimental analysis was performed to find out the possible causes of the higher average propagation loss in Ta2O5 waveguides, some sections being observed with 0.02 dB/cm or lower losses

NASA Tech Briefs, September 1992

Topics include: Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences

Particle Physics Reference Library

This second open access volume of the handbook series deals with detectors, large experimental facilities and data handling, both for accelerator and non-accelerator based experiments. It also covers applications in medicine and life sciences. A joint CERN-Springer initiative, the “Particle Physics Reference Library” provides revised and updated contributions based on previously published material in the well-known Landolt-Boernstein series on particle physics, accelerators and detectors (volumes 21A,B1,B2,C), which took stock of the field approximately one decade ago. Central to this new initiative is publication under full open access

Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridded channel routing. The proposed technique is compared with previous track-oriented techniques, especially a track permutation technique whose performance is bounded by an exhaustive track permutation algorithm. Experiments showed that the presented technique is more effective than the track permutation technique. Keywords - VLSI, coupling capacitance, crosstalk, channel routing, track permutation, segment rearrangement. INTRODUCTION The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. It is known that the coupling capacitance between wires be..

Technology 2004, Vol. 2

Proceedings from symposia of the Technology 2004 Conference, November 8-10, 1994, Washington, DC. Volume 2 features papers on computers and software, virtual reality simulation, environmental technology, video and imaging, medical technology and life sciences, robotics and artificial intelligence, and electronics