Master of Science

thesisAdvances in silicon photonics are enabling hybrid integration of optoelectronic circuits alongside current complementary metal-oxide-semiconductor (CMOS) technologies. To fully exploit the capability of this integration, it is important to explore the effects of thermal gradients on optoelectronic devices. The sensitivity of optical components to temperature variation gives rise to design issues in silicon on insulator (SOI) optoelectronic technology. The thermo-electric effect becomes problematic with the integration of hybrid optoelectronic systems, where heat is generated from electrical components. Through the thermo-optic effect, the optical signals are in turn affected and compensation is necessary. To improve the capability of optical SOI designs, optical-wave-simulation models and the characteristic thermal operating environment need to be integrated to ensure proper operation. In order to exploit the potential for compensation by virtue of resynthesis, temperature characterization on a system level is required. Thermal characterization within the flow of physical design automation tools for hybrid optoelectronic technology enables device resynthesis and validation at a system level. Additionally, thermally-aware routing and placement would be possible. A simplified abstraction will help in the active design process, within the contemporary computer-aided design (CAD) flow when designing optoelectronic features. This thesis investigates an abstraction model to characterize the effect of a temperature gradient on optoelectronic circuit operation. To make the approach scalable, reduced order computations are desired that effectively model the effect of temperature on an optoelectronic layout; this is achieved using an electrical analogy to heat flow. Given an optoelectronic circuit, using a thermal resistance network to abstract thermal flow, we compute the temperature distribution throughout the layout. Subsequently, we show how this thermal distribution across the optoelectronic system layout can be integrated within optoelectronic device- and system-level analysis tools

Center for Space Microelectronics Technology

The 1991 Technical Report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the Center during the past year. The report lists 193 publications, 211 presentations, and 125 new technology reports and patents

Center for space microelectronics technology

The 1992 Technical Report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the center during the past year. The report lists 187 publications, 253 presentations, and 111 new technology reports and patents in the areas of solid-state devices, photonics, advanced computing, and custom microcircuits

Compound Semiconductor Materials and Devices

Contains table of contents for Part I, table of contents for Section 1, an introduction, reports on fourteen research projects and a list of publications.Defense Advanced Research Projects Agency/National Center for Integrated Photonics TechnologyJoint Services Electronics Program Grant DAAH04-95-1-0038MIT Lincoln LaboratoryNational Science Foundation Graduate FellowshipU.S. Navy - Office of Naval ResearchAT&T Bell Laboratories FellowshipU.S. Army - Ft. MeadeNTT CorporationNational Science FoundationLockheed-Martin Corporatio

Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 /spl times/ 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip

Design and characterisation of a ferroelectric liquid crystal over silicon spatial light modulator

Many optical processing systems rely critically on the availability of high performance, electrically-addressed spatial light modulators. Ferroelectric liquid crystal over silicon is an attractive spatial light modulator technology because it combines two well matched technologies. Ferroelectric liquid crystal modulating materials exhibit fast switching times with low operating voltages, while very large scale silicon integrated circuits offer high-frequency, low power operation, and versatile functionality. This thesis describes the design and characterisation of the SBS256 - a general purpose 256 x 256 pixel ferroelectric liquid crystal over silicon spatial light modulator that incorporates a static-RAM latch and an exclusive-OR gate at each pixel. The static-RAM latch provides robust data storage under high read-beam intensities, while the exclusive-OR gate permits the liquid crystal layer to be fully and efficiently charge balanced. The SBS256 spatial light modulator operates in a binary mode. However, many applications, including helmet-mounted displays and optoelectronic implementations of artificial neural networks, require devices with some level of grey-scale capability. The 2 kHz frame rate of the device, permits temporal multiplexing to be used as a means of generating discrete grey-scale in real-time. A second integrated circuit design is also presented. This prototype neuraldetector backplane consists of a 4 x 4 array of optical-in, electronic-out processing units. These can sample the temporally multiplexed grey-scale generated by the SBS256. The neurons implement the post-synaptic summing and thresholding function, and can respond to both positive and negative activations - a requirement of many artificial neural network models

Characterisation of a reconfigurable free space optical interconnect system for parallel computing applications and experimental validation using rapid prototyping technology

Free-space optical interconnects (FSOIs) are widely seen as a potential solution to present and future bandwidth bottlenecks for parallel processing applications. This thesis will be focused on the study of a particular FSOI system called Optical Highway (OH). The OH is a polarised beam routing system which uses Polarising Beam Splitters and Liquid Crystals (PBS/LC) assemblies to perform reconfigurable interconnection networks. The properties of the OH make it suitable for implementing different passive static networks. A technology known as Rapid Prototyping (RP) will be employed for the first time in order to create optomechanical structures at low cost and low production times. Off-theshelf optical components will also be characterised in order to implement the OH. Additionally, properties such as reconfigurability, scalability, tolerance to misalignment and polarisation losses will be analysed. The OH will be modelled at three levels: node, optical stage and architecture. Different designs will be proposed and a particular architecture, Optimised Cut-Through Ring (OCTR), will be experimentally implemented. Finally, based on this architecture, a new set of properties will be defined in order to optimise the efficiency of the optical channels