Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation

Embedded SRAMs can occupy the majority of the chip area in SOCs. The increase in process variation and aging degradation due to technology scaling can severely compromise the integrity of SRAM memory cells, hence resulting in cell failures. Enough cell failures in a memory can lead to it being rejected during initial testing, and hence decrease the manufacturing yield. Or, as a result of long-term applied stress, lead to in-field system failures. Certain types of cell failures can be mitigated through improved timing control. Post-fabrication programmable timing can allow for after-the-fact calibration of timing signals on a per die basis. This allows for a SRAM's timing signals to be generated based on the characteristics specific to the individual chip, thus allowing for an increase in yield and reduction in in-field system failures. In this thesis, a delay line based SRAM timing block with digitally programmable timing signals has been implemented in a 180 nm CMOS technology. Various timing-related cell failure mechanisms including: 1). Operational Read Failures, 2). Cell Stability Failures, and 3). Power Envelope Failures are investigated. Additionally, the major contributing factors for process variation and device aging degradation are discussed in the context of SRAMs. Simulations show that programmable timing can be used to reduce cell failure rates by over 50%

Signal Probability Control for Relieving NBTI in SRAM Cells

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the signal probability. This is because, it is the key parameter of NBTI degradation. Based on the observations, we propose a novel cell-flipping technique in order to make signal probability close to 50%. The long cell-flipping period leads to threshold voltage degradation as large as the original case where the cell-flipping technique is not applied. Thus, we employ the short flipping period to the cell-flipping technique without any stall of operations. In consequence of applying the cell-flipping technique to a register file, we can relieve threshold voltage degradation by 70% after the SRAM cell is used for 3 years

Signal Probability Control for Relieving NBTI in SRAM Cells

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the signal probability. This is because, it is the key parameter of NBTI degradation. Based on the observations, we propose a novel cell-flipping technique in order to make signal probability close to 50%. The long cell-flipping period leads to threshold voltage degradation as large as the original case where the cell-flipping technique is not applied. Thus, we employ the short flipping period to the cell-flipping technique without any stall of operations. In consequence of applying the cell-flipping technique to a register file, we can relieve threshold voltage degradation by 70% after the SRAM cell is used for 3 years

Techniques for Aging, Soft Errors and Temperature to Increase the Reliability of Embedded On-Chip Systems

This thesis investigates the challenge of providing an abstracted, yet sufficiently accurate reliability estimation for embedded on-chip systems. In addition, it also proposes new techniques to increase the reliability of register files within processors against aging effects and soft errors. It also introduces a novel thermal measurement setup that perspicuously captures the infrared images of modern multi-core processors

Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors

Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above