Impact on signal integrity of interconnect variabilities

In this paper, literature results on the statistical simulation of lossy and dispersive interconnect networks with uncertain physical properties are extended to general nonlinear circuits. The approach is based on the expansion of circuit voltages and currents into polynomial chaos approximations. The derivation of deterministic circuit equivalents for nonlinear components allows to retrieve the unknown expansion coefficients with a single circuit simulation, that can be carried out via standard SPICE-type solvers. These coefficients provide direct statistical information. The methodology allows the inclusion of arbitrary nonlinear elements and is validated via transmission-line networks terminated by diodes and driven by inverter

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed

Behavioral modeling of digital IC input and output ports

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to the characterization of actual device