A study of Radiation-Tolerant Voltage-Controlled Oscillators designs in 65 nm bulk and 28 nm FDSOI CMOS technologies

Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices and communications systems that operate in radiation environments, where significant perturbations, especially in terms of phase noise, can be generated due to radiation particles. Among all the blocks that form a PLL system, previous research suggests the voltage-controlled oscillator (VCO) is one of the most critical components in terms of radiation tolerance and electric performance. Ring oscillators (ROs) and LC-tank VCOs have been commonly employed in high-performance PLLs. Nevertheless, both structures have drawbacks including a limited tuning range, high sensitivity to phase noise, limited radiation tolerance, and large design areas. In order to fulfill these high-performance requirements, a current-model logic (CML) based RO-VCO is presented as a possible solution capable of reducing the limitations of the commonly used structures and exploiting their advantages. The proposed hybrid VCO model includes passive components in its design which are the key parameters that define oscillation frequency of this structure. This tunable oscillator has been designed and tested in 65nm Bulk and 28 nm Fully depleted silicon-on-insulator (FDSOI) CMOS technologies The 65nm testchip was designed to compare the behavior of the proposed CML VCO with a current-starved RO and a radiation hardened by design (RHBD) LC-tank VCO in terms of tuning range, phase noise, Single event effect (SEE) sensitivity and design area. Simulations were carried out by applying a double exponential current pulse into different sensitive nodes of the three VCOs. In addition, SEE tests were conducted using pulsed laser experiments. Simulation and test results show that a CML VCO can effectively overcome the limitations presented by a RO-VCO and LC-tank VCO, achieving a wide range of tuning, and low sensitivity to noise and SEEs without the need for a large cross-section. Further studies of the proposed CML VCO were done on 28nm FDSOI in order to reduce the leakage current and increase the switching speed. the same current-starved VCO and CML VCO were implemented on this testchip, and simulations were performed by injecting a double exponential current pulse energy into the previously defined sensitive nodes. The results show SEE sensitivity improvement without narrowing the tuning range or affecting the phase noise response

Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology

Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting in voltage and current perturbation, where errors are induced. This phenomenon is termed a Single Event Effect (SEE). With the shrinking of transistor size, charge sharing between adjacent devices leads to less effectiveness of current radiation hardening methods. Improving fault-tolerance of storage cells and logic gates in advanced technologies becomes urgent and important. A new Single Event Upset (SEU) tolerant latch is proposed based on a previous hardened Quatro design. Soft error analysis tools are used and results show that the critical charge of the proposed design is approximately 2 times higher than that of the reference design with negligible penalty in area, delay, and power consumption. A test chip containing the proposed flip-flop chains was designed and exposed to alpha particles as well as heavy ions. Radiation experimental results indicate that the soft error rates of the proposed design are greatly reduced when Linear Energy Transfer (LET) is lower than 4, which makes it a suitable candidate for ground-level high reliability applications. To improve radiation tolerance of combinational circuits, two combinational logic gates are proposed. One is a layout-based hardening Cascode Voltage Switch Logic (CVSL) and the other is a fault-tolerant differential dynamic logic. Results from a SEE simulation tool indicate that the proposed CVSL has a higher critical charge, less cross section, and shorter Single Event Transient (SET) pulses when compared with reference designs. Simulation results also reveal that the proposed differential dynamic logic significantly reduces the SEU rate compared to traditional dynamic logic, and has a higher critical charge and shorter SET pulses than reference hardened design

Monolithic Integration Piezoelectric Resonators on CMOS for Radio-Frequency and Sensing Applications

Software cognitive radios and Internet of Things (IoT) are recent interest areas that need low loss and low power consumption hardware. More specifically, the area of software cognitive radios requires that hardware be frequency agile and highly selective. Meanwhile, IoT relies on multiple low power sensor networks. By combining Complementary Metal Oxide Semiconductors (CMOS) technology with piezoelectric Micro-Electro-Mechanical Systems (MEMS), we can fabricate Systems-on-Chip (SoC) that can be used as filters or references (oscillators) and highly selective sensors. In this work we developed a die-level compatible process for the monolithic integration of Bulk Acoustic Resonators (BAWs) on CMOS for low power, reduced area and high-quality passives for radio frequency applications. Using CMOS as a fabrication substrate some stringent requirements were added to maintain the dies and the technology’s integrity. A few of these limitations were the need for a low thermal budget fabrication process, die handling and electro-static discharge (ESD) protection. The devices were first fabricated on glass for modeling extraction that was later used for the design of the integrated circuits (IC). Three integrated circuits were designed as substrates for the integration using IBM’s 180nm and TSMC’s 65nm technology. A monolithic BAW oscillator with a resonance frequency of 1.8GHz was demonstrated with an FOM ~186dBc/Hz, comparable to other academia work. Using the developed process, a membrane BAW structure (FBAR) was integrated as well. Using a susceptor coating and zinc oxide’s (ZnO) high temperature coefficient of frequency (TCF) the device was studied as an alternative uncooled infrared sensor. Finally, a reprogrammable IC and an RF PCB were designed for volatile organic compound (VOC) testing using self-assembled monolayers (SAMs) as the absorber layer

Single event effects in 0.18 μm CMOS image sensors

CMOS image sensors are widely used on Earth and are becoming increasingly favourable for use in space. Advantages, such as low power consumption, and ever-improving imaging peformance make CMOS an attractive option. The ability to integrate camera functions on-chip, such as biasing and sequencing, simplifies designing with CMOS sensors and can improve system reliablity. One potential disadvantage to the use of CMOS is the possibility of single event effects, such as single event latchup (SEL), which can cause malfunctions or even permanent destruction of the sensor. These single event effects occur in the space environment due to the high levels of radiation incident on the sensor. This work investigates the ocurrence of SEL in CMOS image sensors subjected to heavy-ion irradiation. Three devices are investigated, two of which have triple-well doping implants. The resulting latchup cross-sections are presented. It is shown that using a deep p well on 18 μm epitaxial silicon increases the radiation hardness of the sensor against latchup. The linear energy transfer (LET) threshold for latchup is increased when using this configuration. Our findings suggest deep p wells can be used to increase the radiation tollerance of CMOS image sensors for use in future space missions

Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

Μελέτη αντοχής στην επίδραση ιονίζουσας ακτινοβολίας τεχνολογίας κατασκευής μικροηλεκτρονικών κυκλωμάτων υψηλής κλίμακας ολοκλήρωσης (65nm) για εφαρμογές σε πειράματα Φυσικής Υψηλών Ενεργειών

Η παρούσα εργασία πραγματοποιήθηκε στην ομάδα Μικροηλεκτρονικής του CERN (Ευρωπαϊκό Εργαστήριο Φυσικής Σωματιδίων), όπου ο Μεγάλος Επιταχυντής Αδρονίων LHC έχει σχεδιαστεί για να επιταχύνει δέσμες πρωτονίων στα 14TeV (στο κέντρο μάζας). Η αναβάθμιση του LHC επιβάλλει σημαντικές προκλήσεις για τους ανιχνευτές, που οφείλονται στη μακρόχρονη λειτουργία και το ραδιενεργό περιβάλλον και συνεπάγεται σημαντικό επανασχεδιασμό των υποανιχνευτών και των αντίστοιχων ηλεκτρονικών μικροκυκλωμάτων, που πρέπει να λειτουργούν μέσα σε ένα πολύ πιο έντονο ραδιενεργό περιβάλλον, όσον αφορά στην ακτινοβολία και να διατηρήσουν ή και να βελτιώσουν την ικανότητά τους για μεγιστοποίηση των δυνατοτήτων μελέτης νέων καναλιών φυσικής. Υπό το φως αυτών των προκλήσεων μια σειρά προσπαθειών έρευνας και ανάπτυξης έχει ήδη ξεκινήσει για την αντιμετώπιση αυτών των θεμάτων. Για το λόγο αυτό μελετήσαμε την αντοχή στην ακτινοβολία της CMOS τεχνολογίας των 65nm, η οποία προσφέρει σημαντικά πλεονεκτήματα από την άποψη της πυκνότητας ολοκλήρωσης και της κατανάλωσης ισχύος σε σχέση με προηγούμενες τεχνολογίες. Τρανζίστορ διαφόρων διαστάσεων σχεδιάστηκαν στο CERN και κατασκευάστηκαν από συνεργαζόμενη εταιρεία. Για την εξέταση της συμπεριφοράς τους σε περιβάλλον ακτινοβολίας ανάλογο του αναβαθμισμένου LHC, τα τρανζίστορ ακτινοβολήθηκαν στο CERN χρησιμοποιώντας ένα μηχάνημα ακτίνων-Χ και σύστημα μέτρησης για δόσεις μέχρι και 200Μrad. Τα αποτελέσματα των ελέγχων παρουσιάζονται σε αυτήν την εργασία.The work presented in this dissertation has been carried out at the Microelectronics Group of CERN, the European Laboratory for Particle Physics, where the Large Hadron Collider LHC is designed to accelerate proton beams at 14TeV (center of mass). The LHC upgrade imposes significant challenges on the detectors, due to its aggressive timescale and harsh environment and entails a major redesign of the subdetectors and relevant electronics, which must function within a much harder radiation environment and preserve or even better improve their ability to maximize the physics opportunities. In the light of these challenges a number of R&D efforts have already begun to address these issues. For this reason we have investigated the radiation hardness with respect to the Total Ionizing Dose (TID) of a 65nm CMOS technology, which offers significant advantages in terms of density and power dissipation over the previous technologies. Single transistor structures of a variety of dimensions were designed at CERN and fabricated in the premises of a cooperative company. In order to examine their behavior in the radiation environment of the upgraded LHC experiments, we performed irradiation of the devices, using an X-ray machine and measuring system, for total doses up to 200Mrad. The test results are presented in this work

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology

Identifying Worst-Case Test Vectors for Delay Failures Induced by Total Dose in Flash- based FPGA

A thesis presented on the effects of space radiation on the flash-based FPGA leading to failure with applying a proposed fault model to identify the worst, nominal and best-case test vectors for each. This thesis analyzed the delay failure induced in a flash-based field programmable gate array (FPGA) by a total-ionizing dose. It then identified the different factors contributing to the amount of delay induced by the total dose in the FPGA. A novel fault model for delay failure in FPGA was developed. This fault model was used to identify worst-case test vectors for delay failures induced in FPGA devices exposed to a total ionizing dose. The fault model and the methodology for identifying worst-case test vectors WCTV were validated using Micro-semi ProASIC3 FPGA and Cobalt 60 radiation facility

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology