Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

High bandwidth low power operational amplifier design and compensation techniques

The need for high bandwidth operational amplifiers (op amp) exists for numerous applications. This need requires research in the area of Op Amp bandwidth extension. The exploited method in this thesis uses a class of compensation called Indirect Feedback Frequency Compensation in which the compensation current is fed back indirectly from the output to an internal high impedance node, to extend the bandwidth of an Op Amp. Among various compensation methods for operational amplifiers, indirect compensation offers potentially large benefits in regards to power to speed trade-off. The indirect compensated Op Amps can exhibit significant improvements in speed over traditional Miller compensated Op Amps and result in much smaller layout size and lower power consumption. However the technique has not been widely used in practice due to a lack of clear design procedure. This thesis develops an analytical description of how indirect compensation works and derives key trade off equations among various specifications. These results provide the insight needed for practically designing operational amplifiers with this technique. Based on the results, a step-by-step design procedure is proposed for an operational amplifier using indirect compensation. To demonstrate the proposed design procedure, a two stage Op Amp is designed. The Op Amp achieved a 2 MHz gain-bandwidth product (GBW) driving a large capacitive load (100 pF). The GBW of the Op Amp was improved by a factor of 10 times compared to the miller compensation scheme. The amplifier documented in this thesis achieved a higher simulated figures-of-merit (FoMs) compared to the state-of-art and can be directly used in integrated systems to achieve higher performance

Multipath feedforward compensated amplifier, related dipole (doublet) compression technique, and other topics

In order to truly realize entire mixed-signal systems on a chip and leverage the benefits of advanced process technologies, new low-voltage compatible amplifier topologies need to be developed.;In this context, a multipath-compensated multistage amplifier is introduced. These structures are compatible with low-voltage supplies because they use horizontal techniques (cascading) rather than vertical techniques (device stacking) to achieve large DC gains. When properly designed, these amplifiers are inherently first-order and do not suffer a reduction in the achievable gain-bandwidth product due to the process of compensation.;The technique relies upon pole-zero cancellation for proper operation. Absent techniques that ensure accurate cancellations, these architectures are not practical for high-speed applications. This is due to the fact that imperfect cancellations result in the appearance of slow-settling components in the transient response. To overcome this problem, structures that inherently ensure accurate cancellation or those that tune themselves to compensate for variations need to be developed.;A tuning strategy for a two-stage multipath-compensated amplifier was developed. It is based upon the observation that if the low-frequency pole leads the zero, the step-response is underdamped. Conversely, if the zero leads the pole, it is overdamped. By sensing the slope of the transient step response after a delay, the relationship between the location of the pole and the zero can be determined. Utilizing this information, a bias current is adjusted to modify the pole\u27s location relative to the zero. The process is repeated many times driving the mismatch down to an acceptable level. The concept was experimentally verified using a prototype fabricated in a 0.25mu CMOS process.;The insight gained in developing a tuning strategy for the two-stage amplifier has led to a methodology for tuning an amplifier with three or more stages. Preliminary simulations predict the technique is viable.;The thesis covers two additional topics as well. The first is a new CAD tool that enables designers to quickly understand the available design tradeoffs by interactive design space exploration. The second topic is a new transresistor circuit whose linearity is comparable to existing transresistors yet offers realizations that are simpler and more compact.*;*This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation). The CD requires the following system requirements: Adobe Acrobat; Microsoft Office; Windows MediaPlayer or RealPlayer; Internet browser; WinZip

Switched-compensation technique in switched-capacitor circuits for achieving fast settling performance

Resolving stability issue is one of the major challenges in designing a perfect op-amp, the most widely used analog circuit block. Many compensation techniques have been proposed to improve the stability performance of op amps, but virtually all these techniques were developed for continuous-time applications and subsequently applied to discrete-time applications (e.g., switched-capacitor circuits). Since the early 1980s, an increasing number of op-amps have been used in switched-capacitor circuits with no special compensation method applied. Consequently, there remains a need to explore the possibility of designing a unique compensation method specifically for switched-capacitor use. A new switched-compensation technique (SCT) is proposed for switched-capacitor circuit applications in which high speed is a critical index of performance. In general, designers must deal with trade-offs among accuracy, speed, and power dissipation. SCT avoids traditional approaches of designing high-speed, high-gain operational amplifiers that are in many cases technology-limited. Instead, it modifies the switched-capacitor circuit structure to use the under-damped response of the system, usually regarded as a drawback. SCT is introduced as a novel solution for achieving fast settling performance and lower quiescent power dissipation while guaranteeing almost equivalent accuracy. SCT can be easily implemented in flip-around switched-capacitor amplifier circuits. This paper explains SCT principle and implementation applied to multiplying-digital-to-analog converters (MDACs) as a proof of concept. Simulation results based on an IBM 0.13um CMOS process are presented. Compared with a conventional switched-capacitor amplifier, a SCT-based implementation reduces the quiescent power consumption by half and settling time within 1% error by 60%

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital converters

Different aspects of power optimization of a high-speed, high-accuracy pipeline Analog-to-Digital Converters (ADCs) are considered to satisfy the current and future needs of portable communication devices. First power optimized design strategies for the amplifiers are introduced. Closed form expressions of power w.r.t settling requirements are presented to facilitate a fair comparison and selection of the amplifier structure. Next a new low offset dynamic comparator has been designed. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors. With simplified amplifier power model along with the use of dynamic comparators, a method to optimize the power consumption of a pipeline ADC with kT/C noise constraint is also developed. The total power dependence on capacitor scaling and stage resolution is investigated for a near-optimal solution.;After considering the power requirements of a pipeline ADC, design and statistical modeling of over-range protection requirements is investigated. Closed form statistical expressions for the over-range requirements are developed to assist in the allocation of the error budgets to different pipeline blocks. A new over-range protection algorithm is also developed that relaxes the amplifier design and power requirements.;Finally, two new CMOS Schmitt trigger designs are proposed which can be used as clock inputs for the pipeline ADC. In the new designs, sizing of the feedback inverters is used for independent trip point control. The new designs have also a modest reduction in sensitivity to process variations along with immunity to the kick-back noise without the addition of path delay

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Frequency compensation of CMOS operational amplifier.

Ho Kin-Pui.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 92-95).Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.4Acknowledgements --- p.5Table of Contents --- p.6List of Figures --- p.10List of Tables --- p.14Chapter Chapter 1 --- Introduction --- p.15Overview --- p.15Objective --- p.17Thesis Organization --- p.17Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19Chapter 2.1.1 --- Input Differential Voltage Range --- p.19Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20Chapter 2.1.4 --- Input Offset Voltage --- p.20Chapter 2.1.5 --- Gain Bandwidth Product --- p.21Chapter 2.1.6 --- Phase Margin --- p.22Chapter 2.1.7 --- Slew Rate --- p.22Chapter 2.1.8 --- Settling Time --- p.23Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24Chapter 2.2.1 --- Overview --- p.24Chapter 2.2.2 --- Miller Compensation --- p.25Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27Chapter 3.1 --- Introduction --- p.27Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28Chapter 3.2.1 --- Circuit Description --- p.29Chapter 3.2.2 --- Small Signal analysis --- p.32Chapter 3.2.3 --- Simulation Results --- p.34Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Frequency Response --- p.39Chapter 4.2.1 --- Gain-bandwidth product --- p.40Chapter 4.2.2 --- Right half complex plane zero --- p.40Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42Chapter 4.3 --- Components Sizing --- p.47Chapter 4.4 --- Circuit Simulation --- p.48Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Working principle of the proposed circuit --- p.54Chapter 5.2.1 --- The introduction of nulling resistor --- p.55Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55Chapter 5.2.3 --- Small Signal Analysis --- p.57Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60Chapter 5.2.6 --- Stability Conditions --- p.63Chapter 5.3 --- Performance Comparison --- p.67Chapter 5.4 --- Conclusion: --- p.70Chapter 5.4.1 --- Circuit Modifications: --- p.70Chapter 5.4.2 --- Advantages: --- p.71Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72Chapter 6.1 --- Introduction --- p.72Chapter 6.2 --- Transistor Layout Techniques --- p.72Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72Chapter 6.2.2 --- Common-Centroid Structure --- p.73Chapter 6.3 --- Layout Techniques of Passive Components --- p.74Chapter 6.3.1 --- Capacitor Layout --- p.74Chapter 6.3.2 --- Resistor Layout --- p.75Chapter Chapter 7 --- Measurement Results --- p.77Chapter 7.1 --- Overview --- p.77Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80Chapter 7.3.3 --- Gain Band width Measurement --- p.81Chapter 7.3.4 --- DC Gain measurement --- p.85Chapter 7.3.5 --- Slew Rate Measurement --- p.87Chapter 7.3.6 --- Phase Margin --- p.88Chapter 7.3.7 --- Performance Summary --- p.89Chapter Chapter 8 --- Conclusions --- p.90Chapter Chapter 9 --- Appendix --- p.9

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively