Computer-Integrated Design and Manufacture of Integrated Circuits

Contains an introduction, principal objectives and accomplishments, reports on two research projects and a list of publications.U.S. Navy Contract N00174-92-Q-013

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP

Does a Nanowire Transistor Follow the Golden Ratio? A 2D Poisson-Schrödinger/3D Monte Carlo Simulation Study

In this work, we observed the signatures of isotropic charge distributions showing the same attributes as the golden ratio (Phi) described in art and architecture, we also present a simulation study of ultra-scaled n-type silicon nanowire transistors (NWT) for the 5nm CMOS application. Our results reveal that the amount of mobile charge in the channel is determined by the device geometry and could also be related to the golden ratio (Phi). We also established a link between the main device characteristics, such as a drive and leakage current, and cross-sectional shape and dimensions of the device. We discussed the correlation between the main Figure of Merit (FoM) and the device variability and reliability

Computer-Integrated Design and Manufacture of Integrated Circuits

Contains an introduction, principal objectives and accomplishments for this chapter's research, reports on two research projects and a list of publications.Defense Advanced Research Projects Agency Contract MDA 972 88-K-0008U.S. Navy Contract N00174-93-C-003

Computer-Aided Fabrication System Structure

Contains reports on one research project.Defense Advanced Research Projects Agency MDA 972 88-K-000

Computer-Integrated Design and Manufacture of Integrated Circuits

Contains research goals and objectives, reports on sixteen research projects and a list of publications.Defense Advanced Research Projects Agency/U.S. Navy Contract N00174-93-K-0035Defense Advanced Research Projects Agency/U.S. Army Contract DABT 63-95-C-0088Multisponsored Projects Industrial/MIT Leaders for Manufacturing Progra

TCAD Simulations and Characterization of High-Voltage Monolithic Active Pixel Sensors

High- Voltage Monolithic Active Pixel Sensors (HV-MAPS) have emerged as a promising technology for silicon tracking detectors in particle physics. HV-MAPS, selected as the foundational technology for the Mu3e Pixel Tracker and under investigation for potential implementation in future detector applications, presents unique design challenges due to its intricate structure and complex electric field distribution. This thesis presents the first comprehensive comparison of Technology Computer-Aided Design (TCAD) simulations and experimental measurements in HV-MAPS. The results show that the simulations correctly describe key experimental parameters like breakdown voltage and explain the loss of hit detection efficiency at the edges and corners of the pixels. The TCAD simulations provide insights into the behavior of the charge collection diode of MuPix8, ALTASPix, and MuPix10 prototypes, facilitating design optimizations. These studies primarily investigated the depletion zone, breakdown voltage and electric field distribution. Additionally, the characterization of MuPix10, using testbeam results, allows for the investigation of the efficiency and cluster size for different angles of incidence of the beam Furthermore, this research examines the impact of diffusion and drift on efficiency and cluster size for different voltage, resistivity, and thickness configurations. The findings of this investigation contribute to an enhanced understanding of HV-MAPS and their potential for developing more efficient and reliable silicon tracking detectors in particle physics experiments

Sensitivity Analysis of Algan/Gan Hemts to Process Variation

A sensitivity analysis of AlGaN/GaN HEMT performance on material and process variations was performed. Aluminum mole fraction, barrier thickness, and gate length were varied ± 5% over nominal values to determine how sensitive simulated device performance was to changes in these 3 parameters. Simulated data was generated with the Synopsys TCAD software suite using a physics-based HEMT model. To validate model performance, simulated data was correlated with experimental data, which consisted of wafer epilayer characterization data as well as DC and small-signal RF device performance data from 1-26 GHz. Trends were observed in the experimental data due to variations in the fabrication process. Epilayer data showed cross-wafer trends in sheet resistance, barrier thickness and Al mole fraction but didn’t show any discernable trends in mobility or sheet carrier concentration. Maximum output current was the only measured performance metric that showed a strong trend across the wafers. Data from two different device geometries on the same wafers were compared to determine whether performance variations across a wafer could be attributed to epilayer variation or device geometry. Variation in power and current gain cutoff frequencies was attributed to differences in the device geometry whereas variations in maximum output current was correlated to sheet resistance and barrier thickness variation. Simulated device performance showed varying sensitivities when ± 5% changes in aluminum mole fraction, barrier thickness, and gate length were made. Al mole fraction and barrier thickness had a large effect on DC output up to 40%, while the gate length only moderately effected DC output by 2-3%. However, of all 3 parameters, changes in gate length had the greatest effect on the RF performance (1-3%) while RF performance was negligibly affected by changes in Al mole fraction and barrier thickness. Although varying these three parameters affects device performance, variation in these three parameters alone is insufficient to accurately account for variations in measured device performance