Resource optimization for fault-tolerant quantum computing

In this thesis we examine a variety of techniques for reducing the resources required for fault-tolerant quantum computation. First, we show how to simplify universal encoded computation by using only transversal gates and standard error correction procedures, circumventing existing no-go theorems. We then show how to simplify ancilla preparation, reducing the cost of error correction by more than a factor of four. Using this optimized ancilla preparation, we develop improved techniques for proving rigorous lower bounds on the noise threshold. Additional overhead can be incurred because quantum algorithms must be translated into sequences of gates that are actually available in the quantum computer. In particular, arbitrary single-qubit rotations must be decomposed into a discrete set of fault-tolerant gates. We find that by using a special class of non-deterministic circuits, the cost of decomposition can be reduced by as much as a factor of four over state-of-the-art techniques, which typically use deterministic circuits. Finally, we examine global optimization of fault-tolerant quantum circuits under physical connectivity constraints. We adapt techniques from VLSI in order to minimize time and space usage for computations in the surface code, and we develop a software prototype to demonstrate the potential savings.Comment: 231 pages, Ph.D. thesis, University of Waterlo

Quantum Computing

Quantum mechanics---the theory describing the fundamental workings of nature---is famously counterintuitive: it predicts that a particle can be in two places at the same time, and that two remote particles can be inextricably and instantaneously linked. These predictions have been the topic of intense metaphysical debate ever since the theory's inception early last century. However, supreme predictive power combined with direct experimental observation of some of these unusual phenomena leave little doubt as to its fundamental correctness. In fact, without quantum mechanics we could not explain the workings of a laser, nor indeed how a fridge magnet operates. Over the last several decades quantum information science has emerged to seek answers to the question: can we gain some advantage by storing, transmitting and processing information encoded in systems that exhibit these unique quantum properties? Today it is understood that the answer is yes. Many research groups around the world are working towards one of the most ambitious goals humankind has ever embarked upon: a quantum computer that promises to exponentially improve computational power for particular tasks. A number of physical systems, spanning much of modern physics, are being developed for this task---ranging from single particles of light to superconducting circuits---and it is not yet clear which, if any, will ultimately prove successful. Here we describe the latest developments for each of the leading approaches and explain what the major challenges are for the future.Comment: 26 pages, 7 figures, 291 references. Early draft of Nature 464, 45-53 (4 March 2010). Published version is more up-to-date and has several corrections, but is half the length with far fewer reference

An addressable quantum dot qubit with fault-tolerant control fidelity

Exciting progress towards spin-based quantum computing has recently been made with qubits realized using nitrogen-vacancy (N-V) centers in diamond and phosphorus atoms in silicon, including the demonstration of long coherence times made possible by the presence of spin-free isotopes of carbon and silicon. However, despite promising single-atom nanotechnologies, there remain substantial challenges in coupling such qubits and addressing them individually. Conversely, lithographically defined quantum dots have an exchange coupling that can be precisely engineered, but strong coupling to noise has severely limited their dephasing times and control fidelities. Here we combine the best aspects of both spin qubit schemes and demonstrate a gate-addressable quantum dot qubit in isotopically engineered silicon with a control fidelity of 99.6%, obtained via Clifford based randomized benchmarking and consistent with that required for fault-tolerant quantum computing. This qubit has orders of magnitude improved coherence times compared with other quantum dot qubits, with T_2* = 120 mus and T_2 = 28 ms. By gate-voltage tuning of the electron g*-factor, we can Stark shift the electron spin resonance (ESR) frequency by more than 3000 times the 2.4 kHz ESR linewidth, providing a direct path to large-scale arrays of addressable high-fidelity qubits that are compatible with existing manufacturing technologies

Fault-tolerant sub-lithographic design with rollback recovery

Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (Pf = 10^-7) in systems with 10^12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme

A SWAP Gate for Spin Qubits in Silicon

With one- and two-qubit gate fidelities approaching the fault-tolerance threshold for spin qubits in silicon, how to scale up the architecture and make large arrays of spin qubits become the more pressing challenges. In a scaled-up structure, qubit-to-qubit connectivity has crucial impact on gate counts of quantum error correction and general quantum algorithms. In our toolbox of quantum gates for spin qubits, SWAP gate is quite versatile: it can help solve the connectivity problem by realizing both short- and long-range spin state transfer, and act as a basic two-qubit gate, which can reduce quantum circuit depth when combined with other two-qubit gates. However, for spin qubits in silicon quantum dots, high fidelity SWAP gates have not been demonstrated due to the requirements of large circuit bandwidth and a highly adjustable ratio between the strength of the exchange coupling J and the Zeeman energy difference Delta E_z. Here we demonstrate a fast SWAP gate with a duration of ~25 ns based on quantum dots in isotopically enriched silicon, with a highly adjustable ratio between J and Delta E_z, for over two orders of magnitude in our device. We are also able to calibrate the single-qubit local phases during the SWAP gate by incorporating single-qubit gates in our circuit. By independently reading out the qubits, we probe the anti-correlations between the two spins, estimate the operation fidelity and analyze the dominant error sources for our SWAP gate. These results pave the way for high fidelity SWAP gates, and processes based on them, such as quantum communication on chip and quantum simulation by engineering the Heisenberg Hamiltonian in silicon.Comment: 25 pages, 5 figures

Study of Single Event Transient Error Mitigation

Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy ground-level demands such as generic, flexible, efficient, and fast, are limited. The classic Triple Modular Redundancy (TMR) method is the most well-known and popular technique in space and nuclear environment. But it leads to more than 200% area and power overheads, which is too costly to implement in ground-level applications. Meanwhile, the coding technique is extensively utilized to inhibit upset errors in storage cells, but the irregularity of combinatorial logics limits its use in SET mitigation. Therefore, SET mitigation techniques suitable for ground-level applications need to be addressed. Aware of the demands for SET mitigation techniques in ground-level applications, this thesis proposes two novel approaches based on the redundant wire and approximate logic techniques. The Redundant Wire is a SET mitigation technique. By selectively adding redundant wire connections, the technique can prohibit targeted transient faults from propagating on the fly. This thesis proposes a set of signature-based evaluation equations to efficiently estimate the protecting effect provided by each redundant wire candidates. Based on the estimated results, a greedy algorithm is used to insert the best candidate repeatedly. Simulation results substantiate that the evaluation equations can achieve up to 98% accuracy on average. Regarding protecting effects, the technique can mask 18.4% of the faults with a 4.3% area, 4.4% power, and 5.4% delay overhead on average. Overall, the quality of protecting results obtained are 2.8 times better than the previous work. Additionally, the impact of synthesis constraints and signature length are discussed. Approximate Logic is a partial TMR technique offering a trade-off between fault coverage and area overheads. The approximate logic consists of an under-approximate logic and an over-approximate logic. The under-approximate logic is a subset of the original min-terms and the over-approximate logic is a subset of the original max-terms. This thesis proposes a new algorithm for generating the two approximate logics. Through the generating process, the algorithm considers the intrinsic failure probabilities of each gate and utilizes a confidence interval estimate equation to minimize required computations. The technique is applied to two fault models, Stuck-at and SET, and the separate results are compared and discussed. The results show that the technique can reduce the error 75% with an area penalty of 46% on some circuits. The delay overheads of this technique are always two additional layers of logic. The two proposed SET mitigation techniques are both applicable to generic combinatorial logics and with high flexibility. The simulation shows promising SET mitigation ability. The proposed mitigation techniques provide designers more choices in developing reliable combinatorial logic in ground-level applications

Resource-efficient high-dimensional subspace teleportation with a quantum autoencoder.

Quantum autoencoders serve as efficient means for quantum data compression. Here, we propose and demonstrate their use to reduce resource costs for quantum teleportation of subspaces in high-dimensional systems. We use a quantum autoencoder in a compress-teleport-decompress manner and report the first demonstration with qutrits using an integrated photonic platform for future scalability. The key strategy is to compress the dimensionality of input states by erasing redundant information and recover the initial states after chip-to-chip teleportation. Unsupervised machine learning is applied to train the on-chip autoencoder, enabling the compression and teleportation of any state from a high-dimensional subspace. Unknown states are decompressed at a high fidelity (~0.971), obtaining a total teleportation fidelity of ~0.894. Subspace encodings hold great potential as they support enhanced noise robustness and increased coherence. Laying the groundwork for machine learning techniques in quantum systems, our scheme opens previously unidentified paths toward high-dimensional quantum computing and networking