Pembuatan Alat Bantu Simulasi Dalam Rangka Perancangan Reconfigurable Manufacturing System Di Industri Manufaktur

Reconfigurable Manufacturing Systems (RMS) is a manufacturing system that has an ability to reconfigure hardware, software and control resources at all on the functional and organizational levels, in order to quickly adjust production capacity and functionality in response to sudden changes in market or in regulatory requirements. This study discusses the development of simulation model in order to design the RMS which is observed based on the production result and the use of production time. This model was made by using the method of object-oriented simulation. From the results of simulation and analysis models can be concluded that the RMS simulation model already contains the rules of the six characteristics of RMS (scalability, convertibility, integrability, modularity, customization and diagnosability) so it can be used as a tool in the design and implementation of RMS in manufacturing industry

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-aware merging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31% and 46% for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52% and 70% for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.</jats:p

ASAM : Automatic Architecture Synthesis and Application Mapping; dl. 3.2: Instruction set synthesis

No abstract

Rapid evaluation of custom instruction selection approaches with FPGA estimation

The main aim of this article is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting the FPGA performance measures of selected custom instructions. We will present a FPGA estimation technique that partitions the high-level representation of custom instructions into clusters based on the structural organization of the target FPGA, while taking into account general logic synthesis principles adopted by FPGA tools. In this work, we have evaluated a widely used graph covering algorithm with various heuristics for custom instruction selection. In addition, we present an algorithm called Refined Largest Fit First (RLFF) that relies on a graph covering heuristic to select non-overlapping superset templates, which typically incorporate frequently used basic templates. The initial solution is further refined by considering overlapping templates that were ignored previously to see if their introduction could lead to higher performance. While RLFF provides the most efficient cover compared to the ILP method and other graph covering heuristics, FPGA estimation results reveals that RLFF leads to the worst performance in certain applications. It is therefore a worthy proposition to equip design flows with accurate FPGA estimation in order to rapidly determine the most profitable custom instruction approach for a given application.</jats:p