17,496 research outputs found

    Federated Robust Embedded Systems: Concepts and Challenges

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    The development within the area of embedded systems (ESs) is moving rapidly, not least due to falling costs of computation and communication equipment. It is believed that increased communication opportunities will lead to the future ESs no longer being parts of isolated products, but rather parts of larger communities or federations of ESs, within which information is exchanged for the benefit of all participants. This vision is asserted by a number of interrelated research topics, such as the internet of things, cyber-physical systems, systems of systems, and multi-agent systems. In this work, the focus is primarily on ESs, with their specific real-time and safety requirements. While the vision of interconnected ESs is quite promising, it also brings great challenges to the development of future systems in an efficient, safe, and reliable way. In this work, a pre-study has been carried out in order to gain a better understanding about common concepts and challenges that naturally arise in federations of ESs. The work was organized around a series of workshops, with contributions from both academic participants and industrial partners with a strong experience in ES development. During the workshops, a portfolio of possible ES federation scenarios was collected, and a number of application examples were discussed more thoroughly on different abstraction levels, starting from screening the nature of interactions on the federation level and proceeding down to the implementation details within each ES. These discussions led to a better understanding of what can be expected in the future federated ESs. In this report, the discussed applications are summarized, together with their characteristics, challenges, and necessary solution elements, providing a ground for the future research within the area of communicating ESs

    CSP channels for CAN-bus connected embedded control systems

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    Closed loop control system typically contains multitude of sensors and actuators operated simultaneously. So they are parallel and distributed in its essence. But when mapping this parallelism to software, lot of obstacles concerning multithreading communication and synchronization issues arise. To overcome this problem, the CT kernel/library based on CSP algebra has been developed. This project (TES.5410) is about developing communication extension to the CT library to make it applicable in distributed systems. Since the library is tailored for control systems, properties and requirements of control systems are taken into special consideration. Applicability of existing middleware solutions is examined. A comparison of applicable fieldbus protocols is done in order to determine most suitable ones and CAN fieldbus is chosen to be first fieldbus used. Brief overview of CSP and existing CSP based libraries is given. Middleware architecture is proposed along with few novel ideas

    The Octopus switch

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    This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

    An efficient scalable scheduling mac protocol for underwater sensor networks

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    Underwater Sensor Networks (UWSNs) utilise acoustic waves with comparatively lower loss and longer range than those of electromagnetic waves. However, energy remains a challenging issue in addition to long latency, high bit error rate, and limited bandwidth. Thus, collision and retransmission should be efficiently handled at Medium Access Control (MAC) layer in order to reduce the energy cost and also to improve the throughput and fairness across the network. In this paper, we propose a new reservation-based distributed MAC protocol called ED-MAC, which employs a duty cycle mechanism to address the spatial-temporal uncertainty and the hidden node problem to effectively avoid collisions and retransmissions. ED-MAC is a conflict-free protocol, where each sensor schedules itself independently using local information. Hence, ED-MAC can guarantee conflict-free transmissions and receptions of data packets. Compared with other conflict-free MAC protocols, ED-MAC is distributed and more reliable, i.e., it schedules according to the priority of sensor nodes which based on their depth in the network. We then evaluate design choices and protocol performance through extensive simulation to study the load effects and network scalability in each protocol. The results show that ED-MAC outperforms the contention-based MAC protocols and achieves a significant improvement in terms of successful delivery ratio, throughput, energy consumption, and fairness under varying offered traffic and number of nodes

    An efficient sparse conjugate gradient solver using a Beneš permutation network

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    © 2014 Technical University of Munich (TUM).The conjugate gradient (CG) is one of the most widely used iterative methods for solving systems of linear equations. However, parallelizing CG for large sparse systems is difficult due to the inherent irregularity in memory access pattern. We propose a novel processor architecture for the sparse conjugate gradient method. The architecture consists of multiple processing elements and memory banks, and is able to compute efficiently both sparse matrix-vector multiplication, and other dense vector operations. A Beneš permutation network with an optimised control scheme is introduced to reduce memory bank conflicts without expensive logic. We describe a heuristics for offline scheduling, the effect of which is captured in a parametric model for estimating the performance of designs generated from our approach
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