PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications

Energy efficiency is a major concern in modern high-performance computing system design. In the past few years, there has been mounting evidence that power usage limits system scale and computing density, and thus, ultimately system performance. However, despite the impact of power and energy on the computer systems community, few studies provide insight to where and how power is consumed on high-performance systems and applications. In previous work, we designed a framework called PowerPack that was the first tool to isolate the power consumption of devices including disks, memory, NICs, and processors in a high-performance cluster and correlate these measurements to application functions. In this work, we extend our framework to support systems with multicore, multiprocessor-based nodes, and then provide in-depth analyses of the energy consumption of parallel applications on clusters of these systems. These analyses include the impacts of chip multiprocessing on power and energy efficiency, and its interaction with application executions. In addition, we use PowerPack to study the power dynamics and energy efficiencies of dynamic voltage and frequency scaling (DVFS) techniques on clusters. Our experiments reveal conclusively how intelligent DVFS scheduling can enhance system energy efficiency while maintaining performance

Scheduling unrelated parallel machines with resource-assignable sequence-dependent setup times

[EN] A novel scheduling problem that results from the addition of resource-assignable setups is presented in this paper. We consider an unrelated parallel machine problem with machine and job sequence-dependent setup times. The new characteristic is that the amount of setup time does not only depend on the machine and job sequence but also on the amount of resources assigned, which can vary between a minimum and a maximum. The aim is to give solution to real problems arising in several industries where frequent setup operations in production lines have to be carried out. These operations are indeed setups whose length can be reduced or extended according to the amount of resources assigned to them. The objective function considered is a linear combination of total completion time and the total amount of resources assigned. We present a mixed integer program (MIP) model and some fast dispatching heuristics. We carry out careful and comprehensive statistical analyses to study what characteristics of the problem affect the MIP model performance. We also study the effectiveness of the different heuristics proposed. © 2011 Springer-Verlag London Limited.The authors are indebted to the referees and editor for a close examination of the paper, which has increased its quality and presentation. This work is partially funded by the Spanish Ministry of Science and Innovation, under the project "SMPA-Advanced Parallel Multiobjective Sequencing: Practical and Theoretical Advances" with reference DPI2008-03511/DPI. The authors should also thank the IMPIVA-Institute for the Small and Medium Valencian Enterprise, for the project OSC with references IMIDIC/2008/137, IMIDIC/2009/198, and IMIDIC/2010/175.Ruiz García, R.; Andrés Romano, C. (2011). Scheduling unrelated parallel machines with resource-assignable sequence-dependent setup times. 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A Graph-Partition-Based Scheduling Policy for Heterogeneous Architectures

In order to improve system performance efficiently, a number of systems choose to equip multi-core and many-core processors (such as GPUs). Due to their discrete memory these heterogeneous architectures comprise a distributed system within a computer. A data-flow programming model is attractive in this setting for its ease of expressing concurrency. Programmers only need to define task dependencies without considering how to schedule them on the hardware. However, mapping the resulting task graph onto hardware efficiently remains a challenge. In this paper, we propose a graph-partition scheduling policy for mapping data-flow workloads to heterogeneous hardware. According to our experiments, our graph-partition-based scheduling achieves comparable performance to conventional queue-base approaches.Comment: Presented at DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (arXiv:1502.07241