Ekstraksi Fitur Conflict of Interest pada Artikel Ilmiah Untuk Menentukan Kualitas Citation Author

Sitasi pada publikasi ilmiah mempengaruhi kualitas artikel sehingga akanberpengaruh terhadap kredibilitas author (peneliti). Terda pat banyak cara untuk meningkatkan kredibilitas peneliti, salah satunya adalah dengan melakukan sitasi terhadap diri sendiri (self citation). Namun, proses self citation yang berlebihan mengurangi kualitas sitasi paper tersebut. Terdapat banyak penelitian yang membuat metode untuk mengukur kualitas self-citation yang tidak sesuai, salah satunya dengan menggunakan rasio self-citation pada jendela waktu. Akan tetapi, metode ini tidak mempertimbangkan kesesuaian topik penelitian paper utama terhadap paper yang mensitasinya. Sehingga diperlukan adanya penentuan kualitas sitasi pada author agar dapat diketahui apakah peneliti sering meggunakan citation yang tidak sesuai topiknya berdasarkan paper author dan paper sitasi. Penelitian ini mengusulkan metode ekstraksi fitur conflict of interest untuk menentukan kualitas citation penulis artikel ilmiah. Hal ini dilakukan untuk mengetahui seberapa baik peneliti dalam menggunakan sitasinya. Terdapat 2 fitur yang diusulkan dalam penelitian ini. Pertama, fitur confict of interest yang didapatkan dari konflik kepentingan antara author paper dan author paper yang disitasi. Kedua, fitur similaritas konten yaitu fitur yang didapatkan dari kesamaan topik antar dokumen paper dan yang disitasinya. Metode similaritas yang digunakan adalah salah satu pendekatan deep learning yaitu Siamese Neural Network yang dikombinasikan dengan Long Short Term Memory. Kedua fitur ini selanjutnya diklasifikasi untuk menentukan kualitas citation author. Seluruh fitur akan diuji performanya pada proses klasifikasi. Hasil klasifikasi selanjutnya akan dihitung nilai akurasinya untuk mendapatkan performa fitur yang diusulkan. Hasil uji coba menunjukkan bahwa usulan fitur dapat digunakan untuk mengklasifikasi kualitas sitasi author. Hal ini ditunjukkan dengan nilai akurasi sebesar 66.67% pada klasifikasi Random Forest dan rata-rata akurasi sebesar 62% pada 3 klasifikasi yang digunakan. =================================================================================================== Citation on scientific paper affect on article quality so that it will affect on author credibility. There are many ways to increase the credibility of researchers, one of them is to do a self-citation. However, this process makes the calculation in bibliometric becoming less accurate because it doesn’t consider citation quality. There is some studies that proposed a method to measure an inappropriate self-citation, one of them is using self-citation ratio. But, this method doesnt consider topic relatedness between main paper and cited paper. So, its required to determine author’s citation quality to know that author are using anomalous citation based on main paper and each cited paper. This research proposed feature extraction conflict of interest to detect author’s citation quality. It allows us to know how right an author use citation in publication. Two features are proposed in this research. First, conflict of interest feature, is obtained from interest conflict between paper author and citation’s paper author. Second, content similarity feature, is obtained from the similarity between paper and cited papers of author. Deep learning approach is used to get the similarity of each document. Combination of Siamese neural network and Long Short-Term Memory can provide a better result on similarity based on training data. Last, all features will be combined with self-citation’s count feature based on previous research and classified to detect author’s citation quality. Features will be tested for its performance using classification. From the classification results, accuracy will be calculated to obtain the performance of the proposed feature. Based on the result, proposed feature can be used to classify author’s citation quality. It is shown with 66,67% of accuracy by using Random Forest classification and 62% of average accuracy on 3 classifier

Approximate logic circuits: Theory and applications

CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's law, has been the thrust behind increasingly powerful integrated circuits for over half a century. As dimensions are scaled to few tens of nanometers, process and environmental variations can significantly alter transistor characteristics, thus degrading reliability and reducing performance gains in CMOS designs with technology scaling. Although design solutions proposed in recent years to improve reliability of CMOS designs are power-efficient, the performance penalty associated with these solutions further reduces performance gains with technology scaling, and hence these solutions are not well-suited for high-performance designs. This thesis proposes approximate logic circuits as a new logic synthesis paradigm for reliable, high-performance computing systems. Given a specification, an approximate logic circuit is functionally equivalent to the given specification for a "significant" portion of the input space, but has a smaller delay and power as compared to a circuit implementation of the original specification. This contributions of this thesis include (i) a general theory of approximation and efficient algorithms for automated synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions based on approximate circuits to improve reliability of designs with negligible performance penalty, and (iii) efficient decomposition algorithms based on approxiiii mate circuits to improve performance of designs during logic synthesis. This thesis concludes with other potential applications of approximate circuits and identifies. open problems in logic decomposition and approximate circuit synthesis

Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.

The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as a way to improve the cost and performance of electronic devices. However, several design challenges have emerged as transistors have become smaller. For instance, wires are not scaling as fast as transistors, and delay associated with wires is becoming more significant. Moreover, in the design flow for integrated circuits, accurate modeling of wire-related delay is available only toward the end of the design process, when the physical placement of logic units is known. Consequently, one can only know whether timing performance objectives are satisfied, i.e., if timing closure is achieved, after several design optimizations. Unless timing closure is achieved, time-consuming design-flow iterations are required. Given the challenges arising from increasingly complex designs, failing to quickly achieve timing closure threatens the ability of designers to produce high-performance chips that can match continually growing consumer demands. In this dissertation, we introduce powerful constraint-guided synthesis optimizations that take into account upcoming timing closure challenges and eliminate expensive design iterations. In particular, we use logic simulation to approximate the behavior of increasingly complex designs leveraging a recently proposed concept, called bit signatures, which allows us to represent a large fraction of a complex circuit's behavior in a compact data structure. By manipulating these signatures, we can efficiently discover a greater set of valid logic transformations than was previously possible and, as a result, enhance timing optimization. Based on the abstractions enabled through signatures, we propose a comprehensive suite of novel techniques: (1) a fast computation of circuit don't-cares that increases restructuring opportunities, (2) a verification methodology to prove the correctness of speculative optimizations that efficiently utilizes the computational power of modern multi-core systems, and (3) a physical synthesis strategy using signatures that re-implements sections of a critical path while minimizing perturbations to the existing placement. Our results indicate that logic simulation is effective in approximating the behavior of complex designs and enables a broader family of optimizations than previous synthesis approaches.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/61793/1/splaza_1.pd

A new enhanced SPFD rewiring algorithm

This paper presents an in-depth study of the theory and algorithms for the SPFD-based (Set of Pairs of Functions to be Distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70 % higher than SPFD-based local rewiring algorithms (SPFD-LR) [19][21] and 18 % higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR)[20]. (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we study the impact of using different atomic SPFD pair assignment methods during the SPFD-based rewiring. We develop several heuristic atomic SPFD pair assignment methods for area or delay minimization and show that they lead to 10 % more selected rewiring ability than the random (or arbitrary) assignment methods. When combining (1) and (2) together, we can achieve 38.1 % higher general rewiring ability. 1

SPFD-Based Global Rewiring

This paper presents the theory and algorithm for SPFD-based global rewiring (SPFD-GR). SPFD-GR allows us to globally replace a target wire with some alternative wire possibly far away from the target. It successfully overcomes the limitations of the existing SPFD-based local rewiring algorithm (SPFD-LR), which can only replace a wire with another wire that has the same destination node. In order to perform SPFD-based global rewiring, we developed the theory and algorithm for solving a fundamental problem in SPFD-based rewiring: Given the in-pin functions of a node and the SPFD at the node's out-pin, is there a way to modify the node's internal function so that the SPFD at the node's out-pin can be satisfied? Combined with a state-of-the-art partitioning algorithm, SPFD-GR scales well to large circuits with good synthesis quality. Our SPFD-based rewiring algorithm is ideal for LUT-based FPGAs, where the node's internal function can be changed freely without any area or delay penalty. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of SPFD-GR (in terms of the number of wires that have alternative wires) is 1.45, and 3 times that of SPFD-LR and an ATPG-based rewiring algorithm (with a preliminary experimental flow), respectively, while the run time is quite acceptable. When applied to the post-mapping area reduction for large LUT-based FPGAs under circuit depth restriction, SPFD-GR achieves 17.1% average area reduction, with no or little delay increase