MEMS suljenta kuparin lämpöpuristusliitännällä

Copper thermocompression is a promising wafer-level packaging technique, as it allows the bonding of electric contacts simultaneously to hermetic encapsulation. In thermocompression bonding the bond is formed by diffusion of atoms from one bond interface to another. The diffusion is inhibited by barrier forming surface oxide, high surface roughness and low temperature. Aim of this study was to establish a wafer-level packaging process for MEMS (Mi-croElectroMechanical System) mirror and MEMS gyroscope. The cap wafer of the MEMS mirror has an antireflective coating that limits the thermal budget of the bonding process to 250°C. This temperature is below the eutectic temperature of most common eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C). Thus a thermocompression bonding method needed to be developed. Copper was used as a bonding material due to its low cost, high self-diffusivity and resistance to oxidation in ambient air. The bond structures were fabricated using three different methods and the bonding was further enhanced by annealing. The bonded structures were characterized with scanning acoustic microscopy, scanning electron microscope and the bond strength was determined by shear testing. Exposing the bond structures to etchant during Cu seed layer removal was found to drastically increase the surface roughness of bond structures. This increase proved detrimental to bond strength and dicing yield and thus covering the bond surface during wet etching is recommended. The native oxidation on copper surfaces was completely removed with combination of ex situ acetic acid wet etch and in situ forming gas anneal. Successful thermocompression bonding process using sputtered copper films was established at a low temperature of 200°C, well below the thermal limitation set by the antireflective coating. The established wafer bonding process had high yield of 97% after dicing. The bond strength was evaluated by maximum shear strength and recorded at 75 MPa, which is well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa.Kuparin lämpöpuristusliitäntä on lupaava kiekkotason pakkausmenetelmä, sillä se mahdollistaa sekä sähköisten liitäntöjen, että hermeettisen suljennan toteuttamisen samanaikaisesti. Lämpöpuristusliitännässä sidos muodostuu atomien diffuusiosta liitospinnalta toiselle. Diffuusiota rajoittavat estokerroksen muodostava pinta oksidi, korkea pinnan karheus ja matala lämpötila. Diplomityön tavoitteena oli luoda kiekkotason pakkausmenetelmä mikroelektromekaaniselle (MEMS, MicroElectroMechanical System) peilille ja MEMS gyroskoopille. Peilin lasisen kansikiekon pinnalla oleva antiheijastava kalvo rajoitti liitännässä käytettävän lämpötilan korkeintaan 250°C:een, mikä on alempi lämpötila kuin useimpien kiekkoliitännässä käytettyjen materiaaliparien eutektinen piste. Esimerkkinä mainittakoon mm. Au-Sn (278°C), Au-Ge (361°C) ja Au-Si (370°C). Kuparin alhainen hinta, korkea ominaisdiffuusio ja hidas hapettuminen ilmakehässä puoltavat sen valintaa liitäntämateriaaliksi. Liitäntärakenteet valmistettiin kolmella menetelmällä ja liitännän vahvuutta parannettiin lämpökäsittelyllä. Liitetyt rakenteet karakterisoitiin pyyhkäisy elektronimikroskoopin, akustisen mikroskoopin ja liitoslujuus-mittauksen avulla. Liitospintojen altistamisen hapolle havaittiin lisäävän pinnankarkeutta ja olevan siten haitallista liitokselle ja laskevan saantoa. Liitospintojen suojaaminen siemenkerroksen syövytyksen aikana on suotavaa. Pintaoksidi pystytään poistamaan täysin suorittamalla oksidin märkäetsaus jääetikalla sekä lämpökäsittely N2/H2 atmosfäärissä. Sputteroidut kuparikalvot pystyttiin liittämään onnistuneesti yhteen 200°C lämpötilassa, mikä on alle anti-heijastavan pinnan asettaman lämpötilarajan. Tällä liitäntä menetelmällä saavutettiin kiekkoliitoksella yhteen liitettyjen sirujen sahauksessa korkea 97% saanto. Liitoslujuus määritettiin maksimi-leikkausvoiman avulla ja sen suuruudeksi mitattiin 75 MPa. Lujuus oli yli kymmenkertainen MIL-STD-883E standardin (METHOD 2019.5) asettamaan hylkäysrajaan 6.08 MPa nähden

Bulk-micromachined mass airflow sensor fabrication and testing methodology for an undergraduate microfabrication course.

In July 1995, National Science Foundation Award # 9551869 funded the development of a new inter-disciplinary microfabrication course under the primary leadership of Dr. Kevin Walsh at the University of Louisville. Along with this award, the completed construction of a new building in 1996 that contained a class 1000/100 cleanroom laboratory facilitated the development of the course. Moreover, curricula had to be completed to provide students with practical, hands-on experience in building Micro Electro-Mechanical Systems (MEMS) devices using processes and methodologies introduced in the course. Dr. Walsh wanted to include a mass airflow sensor in his portfolio of total possible devices students could build in the cleanroom lab for the course. This document describes the design of a bulk-micromachined, monolithic, mass airflow sensor with a thermally-isolated, thin-film, dielectric, microbridge/diaphragm design. In addition, several fabrication methodologies were explored, as well as a means to test and evaluate the sensors for this undergraduate class laboratory. The mass airflow sensor architecture chosen was based upon a closed-loop-control,microelectronic thermal (hot-wire) anemometer design, which was first developed and presented by Johnson, Higashi, et. al. at Honeywell in the mid 1980s [2]. Two separate photomask sets were developed using L-Edit™ software (by Tanner Research), with each set including multiple geometric variations of a dual/triple microbridge/cantilever flow sensor structure to be suspended over a precision, anisotropically-etched pit, integrated onto a (100) silicon substrate. Four primary structural fabrication strategies were explored to produce the thin-film material for the flow sensors: (1) RF planar magnetron sputter-deposited 1 m m -thick silicon nitride microbridges/cantilevers; (2) anodically-bonded-and-machined 20-30 m m -thick borosilicate glass diaphragms; (3) spin-on-glass microbridges/cantilevers; and (4) low-stress, 0.5 m m -thick, LPCVD silicon nitride microbridges/cantilevers. Four resistor metallizations were separately evaluated: permalloy (Ni81Fe19), chromium, titanium, and platinum. A process was developed and documented to successfully fabricate flow sensors with low stress LPCVD silicon nitride microbridges/cantilevers. DC planar magnetron sputterdeposited platinum thin-film resistors (with a ~120 nm-thick RF planar magnetron sputterdeposited chromium adhesion layer), with nominal thicknesses of ~56 – 70 nm, were delineated by photolithographic imaging techniques. The resistors had measured Temperature Coefficients of Resistance (TCR) in the range of 1.93 – 2.25 x10-3 W /W /°C at 25 - 125 °C. Anisotropic KOH etching of the (100)-oriented silicon substrate was utilized to release the flow sensor microbridge/cantilever microstructures. After designing and building a flow sensor test machine capable of controlled volumetric air flow rates of up to ~15 SLPM (0.54 m/s), nominal sensor sensitivities (SV) of up to 0.67 mV/SLPM (20.4 mV/(m/s)) were measured. The sensitivities varied somewhat depending upon resistor values set in the flow sensor heater-driver circuit and the insertion depth of the devices within the flow channel

In-situ resonant band engineering of solution-processed semiconductors generates high performance n-type thermoelectric nano-inks.

Thermoelectric devices possess enormous potential to reshape the global energy landscape by converting waste heat into electricity, yet their commercial implementation has been limited by their high cost to output power ratio. No single "champion" thermoelectric material exists due to a broad range of material-dependent thermal and electrical property optimization challenges. While the advent of nanostructuring provided a general design paradigm for reducing material thermal conductivities, there exists no analogous strategy for homogeneous, precise doping of materials. Here, we demonstrate a nanoscale interface-engineering approach that harnesses the large chemically accessible surface areas of nanomaterials to yield massive, finely-controlled, and stable changes in the Seebeck coefficient, switching a poor nonconventional p-type thermoelectric material, tellurium, into a robust n-type material exhibiting stable properties over months of testing. These remodeled, n-type nanowires display extremely high power factors (~500 µW m-1K-2) that are orders of magnitude higher than their bulk p-type counterparts

Thermal dissipation improvement by new technology approach: study, development and characterization

Semiconductor manufacturing requires a silicon substrate to build devices on its front side. The wafer must be thick enough to ensure a stable support during the processing steps. Since the active region of a semiconductor device is limited at the substrate surface, there is a large unused material amount. The material excess causes heat increasing during the operation of the devices. Once the Frond End of Line is completed, the excess material must be removed. Nowadays, there are different thinning techniques adopted in order to reduce the thermal resistance. The thesis project idea is the thermal dissipation improvement with a different approach: instead of reducing the wafer thickness, the adopted technology is exploiting the excess material as a heat sink. The realization of this intrinsic heat sink is achieved by the developing of a suitable process flow, which involves the selective dry etching of the silicon bulk and the subsequent electrodeposition of thick copper. This new process flow offers the advantage of maintaining the wafer “self-support” and allow working with already existing technologies saving on both dedicated thinning technologies and handling technologies. Furthermore, this new approach permits the thermal resistance improvement of semiconductor devices if compared to the standard devices

Molecular level interactions of large area 2D materials

textTwo-dimensional materials such as self-assembled monolayers (SAMs), graphene, etc. are candidate materials for improving the performance of microelectronics components and MEMS/NEMS devices. In view of their relatively large in-plane dimensions, surface forces are likely to dominate their behavior. The purpose of the current work was to extract not only the adhesion energy (or steady state fracture toughness) but also the traction-separation relation associated with interactions between various two-dimensional materials and substrates. In particular, interactions between SAMs terminated by carboxyl and diamine (COOH/NMe2) groups, hydroxylated silicon surfaces, graphene and silicon, graphene and its seed copper and graphene and epoxy over large areas was considered. Traction-separation relations, which are a continuum description of such molecular interactions, were determined by a direct method, which makes use of measurements of crack tip opening displacements; an inverse approach where the key parameters are extracted by comparing measured global parameters with finite element solutions and a hybrid approach in which the direct method was supplemented by finite element analysis. Furthermore, the surface free energy of graphene was measured by contact angle measurements. The most striking observation across all the interactions that were considered is that the interaction ranges were much larger than those attributed to van der Waals forces. While van der Waals models might have been at play between graphene and its seed copper foil and graphene and epoxy, the adhesion energies were surprisingly high. This coupled with the long interaction range suggests that roughness effects modulated the basic force field. Interactions between graphene and silicon and hydroxylated silicon surfaces may have been due to capillary and/or electrostatic again possibly modulated by roughness. The interactions between COOH and NMe2 SAMs became stronger under vacuum, which may have induced chemical bonding, and tougher under mixed-mode loading.Engineering Mechanic

Copper wafer bonding in three-dimensional integration

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 165-176).Three-dimensional (3D) integration, in which multiple layers of devices are stacked with high density of interconnects between the layers, offers solutions for problems when the critical dimensions in integrated circuits keep shrinking. Copper wafer bonding has been considered as a strong candidate for fabrication of three-dimensional integrated circuits (3-D IC). This thesis work involves fundamental studies of copper wafer bonding and bonding performance of bonded interconnects. Copper bonded wafers exhibit good bonding qualities and present no original bonding interfaces when the bonding process occurs at 400⁰C/4000 mbar for 30 min, followed by nitrogen anneal at 400⁰C for 30 min. Oxide distribution in the bonded layer is uniform and sparse. Evolution of microstructure morphologies and grain orientations of copper bonded wafers during bonding and annealing were studied. The bonded layer reaches steady state after post-bonding anneal. The microstructure morphologies and bond strengths of copper bonded wafers under different bonding conditions were investigated.A map summarizing these results provides a useful reference on process conditions suitable for three-dimensional integration based on copper wafer bonding. Similar microstructure morphology of copper bonded interconnects was observed to that of copper bonded wafers. Specific contact resistances of bonded interconnects of approximately 10⁻⁸ [ohms]-cm² were measured by using a novel test structure which can eliminate the errors from misalignment during bonding. The bonding qualities of different interconnect sizes and densities have been investigated. In addition to increasing the bonding temperature and duration, options such as larger interconnect sizes, total bonding area, or use of dummy pads for bonding in the unused area improve the quality of bonded interconnects. Process development of silicon layer stacking based on Cu wafer bonding was successfully applied to demonstrate a strong four-layer-stack structure.Bonded Cu layers in this structure become homogeneous layers and do not show original bonding interfaces. This process can be reliably applied in three-dimensional integration applications.by Kuan-Neng Chen.Ph.D

SYNTHESIS AND CHARACTERIZATION OF NANOSCALE POLYMER FILMS GRAFTED TO METAL SURFACES

Anchoring thin polymer films to metal surfaces allows us to alter, tune, and control their biocompatibility, lubrication, friction, wettability, and adhesion, while the unique properties of the underlying metallic substrates, such as magnetism and electrical conductivity, remain unaltered. This polymer/metal synergy creates significant opportunities to develop new hybrid platforms for a number of devices, actuators, and sensors. This present work focused on the synthesis and characterization of polymer layers grafted to the surface of metal objects. We report the development of a novel method for surface functionalization of arrays of high aspect ratio nickel nanowires/micronails. The polymer \u27grafting to\u27 technique offers the possibility to functionalize different segments of the nickel nanowires/micronails with polymer layers that possess antagonistic (hydrophobic/hydrophilic) properties. This method results in the synthesis of arrays of Ni nanowires and micronails, where the tips modified with hydrophobic layer (polystyrene) and the bottom portions with a hydrophilic layer (polyacrylic acid). The developed modification platform will enable the fabrication of switchable field-controlled devices (actuators). Specifically, the application of an external magnetic field and the bending deformation of the nickel nanowires and micronails will make initially hydrophobic surface more hydrophilic by exposing different segments of the bent nanowires/micronails. We also investigate the grafting of thin polymer films to gold objects. The developed grafting technique is employed for the surface modification of Si/SiO2/Au microprinted electrodes. When electronic devices are scaled down to submicron sizes, it becomes critical to obtain uniform and robust insulating nanoscale polymer films. Therefore, we address the electrical properties of polymer layers of poly(glycidyl methacrylate) (PGMA), polyacrylic acid (PAA), poly(2-vinylpyridine) (P2VP), and polystyrene (PS) grafted to the Si/SiO2/Au microprinted electrodes. The polymer layers insulated under normal ambient conditions can display a significant increase in conductivity as the environment changes. Namely, we demonstrate that the in-plane electrical conductivity of the grafted polymer layers grafted to Au and SiO2 surfaces can be changed by at least two orders of magnitude upon exposure to water or organic solvent vapors. The conductive properties of all the grafted polymer films under study are also significantly enhanced with temperature increase. The observed phenomenon makes possible the chemical design of polymer nanoscale layers with reduced or enhanced sensitivity to anticipated changes in environmental conditions. Finally, we show that the observed effects can be used in a micron-sized conductometric-transducing scheme for the detection of volatile organic solvents. This research also includes the study of nanoscale-level actuation with grafted polymer films and polymer/gold nanoparticles systems-grafted composites. First, we investigate the nanoscale-level actuation with polymer films. To this end, we use \u27grafting to\u27 approach to synthesize PGMA thin polymer film (80-200 nm). Then, film is swollen in a good solvent and freeze-dried until the solvent is sublimated, thereby creating grafted polymer nanofoam that exhibits shape memory properties. We demonstrate nanoscale actuation using the developed system. In addition, we show that the modification of the PGMA nanofoam with low molecular weight polystyrene allows response tuning of the porous polymer film. Furthermore, we incorporate gold nanoparticles (5 nm) into a thin PGMA layer (80 nm) to fabricate a PGMA/gold nanoparticles grafted composite film. The PGMA/gold nanoparticles grafted nanofoam is synthesized following the same procedure developed for the fabrication of the PGMA nanofoam. We demonstrate the shape-memory properties and nanoscale-level actuation of the developed system. Moreover, we investigate the change in the optical signal of the developed system as a function of temperature arising from the localized surface plasmon resonance and plasmon coupling effects of the gold nanoparticles. We envision that the change in optical properties upon actuation can be utilized to develop platforms for new off-line sensing devices

3-5족 화합물 반도체의 웨이퍼 접합과 에피택셜 리프트 오프를 통한 다중 파장 광 검출기

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 재료공학부, 2019. 2. 윤의준.Group III-V compound semiconductors, having a band gap from ultraviolet to infrared regions, have been widely used as imagers to visualize a single band. With the recent arrival of the Internet-of-things (IOTs) era, new applications such as time of flight (TOF) sensors, normalized difference vegetation index (NVDI) and night vision systems have gained interest. Therefore, the importance of multicolor photodetectors is raised. To implement multicolor photodetectors, an epitaxy method has been commonly used with III-V compound semiconductors. For example, quantum wells, quantum dots and type-II based structures and metamorphically grown bulk heteroepitaxial structures have been employed. Although an epitaxy method seems to be quite simple, there are several problems including limitation of material choice due to the discrepancy of lattice constants between thin films and substrates, performance degradation originated from internal defects and complexity of growth. Therefore, to avoid these disadvantages of the epitaxy method, a heterogeneous integration method has been an alternative because the integration of devices grown on different substrates is possible. Thus, it has been considered to be a promising method to combine photodetectors with simple bulk structures. However, although there is a significant advantage to the heterogeneous integration method, current multicolor photodetectors have exhibited limitations regarding pixel density and vertical misalignment due to problems related to conventional integration methods. Therefore, in this thesis, the heterogeneous integration of III-V compound semiconductors was investigated for fabricating multicolor photodetectors with high pixel density and highly accurate alignment. Firstly, a research on heterogeneous integration of GaAs based thin film devices with other substrates was carried out. We studied wafer bonding and epitaxial lift off process which have advantages including large area transferability, cost-effectiveness and high quality of layers compared with wafer splitting and transfer printing methods. To fabricate multicolor photodetectors on single substrates, a stable rigid-to-rigid heterogeneous integration method is highly required. However, there have only been few reports regarding rigid-to-rigid transfer by using epitaxial lift off due to the difficulty involving byproducts and gas bubbles generated during the wet etching of the sacrificial layer for wafer separation. This has been a hindrance compared with thin film on flexible substrates which can accelerate wafer separation by using strain and external equipment. In order to overcome this problem, high throughput epitaxial lift off process was proposed through a pre-patterning process and surface hydrophilization. The pre-patterning process can maximize the etching area of the AlAs sacrificial layer and rapidly remove bubbles. In addition, acetone, which is a hydrophilic solution, was mixed with hydrofluoric acid in order to reduce the surface contact angle and viscosity. It resulted in an effective penetration of the etching solution and the suppression of byproducts. Consequently, it was possible to transfer GaAs thin films on rigid substrates within 30 minutes for a 2 inch wafer which has been the fastest compared with previous reports. Also, using this template, electronic and optoelectronic devices were successfully fabricated and operated. Secondly, we have studied to overcome restrictions of bulk photodetector for InSb binary material including the detection limit and cryogenic operation. To extend the detection limit of bulk InSb toward the LWIR range, the ideal candidate of III-V bulk materials is indium arsenide antimonide (InAsSb) material due to its corresponding band gaps ranging from SWIR to LWIR. By combining bulk InAsSb with other bulk materials with previously developed integration methods, we could ultimately fabricate a multicolor photodetector ranging from ultraviolet to LWIR with only bulk structures. Thus, in order to verify the viability of this material, a p-i-n structure based photodetector with an InAs0.81Sb0.19 absorption layer was grown on a GaAs substrate. To enhance an ability to be operated at a high temperature, an optimum InAlSb barrier layer was designed by technology computer aided design (TCAD). Also, InAsSb/InAlSb heterojunction photodetector was grown by molecular beam epitaxy (MBE). As a result, we have demonstrated the first room temperature operation of heterojunction photodetectors in MWIR range among InAsSb photodetectors with similar Sb compositions. Additionally, it has a higher responsivity of 15 mA/W compared with commercialized photodetectors. This MWIR photodetector with room temperature operability could help the reduction of the volume for final detector systems due to the elimination of Dewar used in InSb photodetectors. In other words, from this experiments, it is suggested that there is a strong potential of InAsSb bulk structures for detecting LWIR. Finally, the study on the monolithic integration was carried out to verify the feasibility of multicolor photodetectors by integration of bulk structures. Among procured photodetectors with detection ranging from visible to MWIR at room temperature operation, visible GaAs and near-infrared InGaAs photodetector were used for establishing the optimized fabrication process due to materials process maturity. By using previously developed high throughput ELO process, GaAs photodetectors were transferred onto InGaAs photodetectors to form visible/near-infrared multicolor photodetectors. It was found that top GaAs PD and bottom InGaAs PD were vertically well aligned without an off-axis tilt in x-ray diffraction (XRD) measurement. Also, similar dark currents of each photodetector were observed compared with reference photodetectors. Finally, with incidence of laser illumination, photoresponses were clearly revealed in visible band and near-infrared band of material characteristics, respectively. These results suggested high throughput ELO process enables the monolithic integration of bulk based multicolor photodetectors on a single substrate with high pixel density and nearly perfect vertical alignment. In the future, depending on the target applications, photodetectors with desired wavelengths could be simply grown as bulk structures and fabricated for multicolor imagers.자외선부터 적외선 영역의 밴드갭을 가진 3-5족 화합물 반도체는 단일 파장대역을 시각화하는 imager 로 널리 사용되고 있다. 그러나, 최근 사물인터넷 시대가 도래함에 따라, time of flight (TOF) 센서, 식생지수 측정, night vision 등의 새로운 응용처가 증가하고 있다. 따라서 기존의 단일파장 광 검출기가 아닌, 다중파장 광 검출기의 중요성이 증대되고 있으며, 이런 다중파장 광 검출기를 구현하기 위해서 3-5족을 화합물 반도체의 epitaxy 방법이 흔히 사용되어 왔다. 예를 들어, 다른 격자 상수를 가진 벌크 구조를 metamorphic 성장법을 이용하여 성장하거나, 또는 양자우물, 양자점 그리고 type-II 기반의 구조가 적용되어야만 했다. Epitaxy 방법은 매우 간단한 방법처럼 보이지만, 기판과 성장하려는 물질간의 격자상수의 차이로 인해 제한되는 물질 선택, 내부 결함에 의한 성능감소 그리고 성장의 복잡함 등 여러 문제가 존재한다. 그래서, epitaxy 방법의 단점들을 회피하기 위하여, 다른 기판에서 성장된 소자의 집적을 가능하게 할 수 있는, 이종 집적 방법이 대안이 되어왔다. 이를 이용하면, 간단한 벌크 구조의 광 검출기를 결합할 수 있기 때문에 매우 유망한 방법으로 여겨지고 있다. 그러나, 이종 집적 방법의 뛰어난 장점에도 불구하고, 현재의 다중파장 광 검출기는 집적 방법의 문제로 수직 정렬 오차 및 픽셀 밀도 측면에서 한계점을 보여주었다. 따라서, 본 논문에서는 고밀도/ 고정렬된 다중파장 광 검출기 제작을 위한 3-5족 기반의 화합물 반도체의 이종 집적 방법에 대한 연구를 진행하였다. 먼저, 3-5족 GaAs 기반의 박막소자를 다른 기판과 이종 집적하는 연구를 수행하였다. 기존의 wafer splitting 과 transfer printing 방법과 비교했을 때 대면적 전사, 저렴한 가격 그리고 고품질 layer등 장점들이 있는 웨이퍼 접합과 에피택셜 리프트 오프 (epitaxial lift off) 방법에 대해서 연구를 하였다. 단일 기판상에 다중파장 광 검출기를 제작하기 위해서는, rigid-to-rigid 이종 집적 방법이 반드시 필요하다. 그러나, strain 과 외부 장치를 이용하여 기판 분리를 가속화 시킬 수 있는 유연기판 상의 박막전사와 달리, 습식 식각 시 생성되는 부산물들과 가스 기포들 때문에 에피택셜 리프트 오프 방법을 이용한 rigid-to-rigid 전사에 대해서는 매우 적은 결과만이 보고되었다. 이런 문제를 극복하기 위해서, pre-patterning 과정과 표면 친수화를 통한 고속 에피택셜 리프트 오프를 제안하였다. 이 pre-patterning 과정은 AlAs 희생층의 식각 영역을 극대화 시킬 수 있으며, 기포를 빠르게 제거할 수 있다. 그리고, 친수성 용액인 아세톤을 불산과 섞어주면 점도와 표면 접촉 각을 줄일 수 있다. 이것은 식각 용액의 효과적인 침투와 부산물을 억제시키는 결과를 보였다. 결과적으로, 2 인치 크기의GaAs 기반 박막들을 rigid 기판상에 30분 이내로 전사가 가능했으며 이는 기존의 보고들과 비교했을 때 가장 빠른 결과이다. 또한 이 템플릿을 이용하여 광/전자 소자를 성공적으로 제작 및 동작시켰다. 두 번째로, 기존의 InSb 물질을 이용한 벌크 구조의 광 검출기가 가진 파장한계 그리고 저온동작 등의 제약들을 극복하기 위한 연구를 진행하였다. 벌크 구조의 파장 한계를 원적외선 대역까지 늘이기 위한, 3-5족 물질 중 이상적인 물질은 인듐 아세나이드 안티모나이드 (indium arsenide antimonide) 이다. 왜냐하면 InAsxSb1-x는 SWIR 부터 LWIR 의 해당하는 밴드 갭을 가지고 있기 때문이다. 이 물질 기반의 구조와 개발된 공정을 사용하면, 우리는 궁극적으로 자외선부터 원적외선까지의 영역을 벌크 구조만을 사용하여 다중파장 광 검출기를 구현할 수 있게 된다. 따라서, 이 물질의 가능성을 검증하기 위해서, InAs0.81Sb0.19 의 흡수층을 가진 p-i-n 구조 기반의 광 검출기를 GaAs 기판상에서 성장하였다. 고온에서 동작 특성을 향상시키기 위하여, 최적의 InAlSb 배리어를 TCAD로 디자인하였다. 이러한, InAsSb/InAlSb 이종 접합 광 검출기는 분자선 증착 장비를 이용하여 성장되었다. 그 결과로, 우리는 비슷한 Sb 조성을 가진 InAsSb 기반의 광 검출기들 중에서, 처음으로 중적외선 대역의 이종 접합 구조의 광 검출기를 상온 동작 하는 것을 시연하였다. 게다가, 그것은 상용화 된 광 검출기보다 높은 광 응답 특성(15 mA/W)을 보여주었다. 이 상온에서 동작하는 중적외선 광 검출기는 InSb 광 검출기에 사용되는 Dewar 를 제거함으로써, 최종 검출기 시스템의 부피를 감소 시킬 수 있다. 이 실험으로부터, 벌크 구조로 원적외선 대역을 검출하기 위한 InAsSb 물질의 큰 잠재성이 있다는 것을 의미한다. 마지막으로, 벌크 구조의 집적을 통한 다중파장 광 검출기의 실현이 가능한지 확인하기 위해서 모놀리식(monolithic) 집적에 관한 연구를 수행하였다. 확보된 상온 동작이 가능한 가시광선부터 MWIR 검출 파장을 가진 광 검출기들 중에서, 최적의 제작 순서를 확립하기 위해서 물질에 관한 성숙도가 높은 가시광선 GaAs 그리고 근적외선 InGaAs 광 검출기를 사용하였다. 가시광/근적외선 대역의 다중파장 광 검출기를 형성하기 위해서, GaAs 광 검출기를 InGaAs 광 검출기 상으로 개발된 고속 에피택셜 리프트 오프 기법을 사용하여 전사하였다. GaAs 광 검출기와 InGaAs 광 검출기는 off-axis 없이 수직으로 잘 정렬되었음을 x-ray 분광법을 이용하여 확인하였다. 또한, 각각의 광 검출기의 기준 소자들과 비교했을 때 비슷한 암 전류가 나타났다. 마지막으로, 레이저 입사를 통해, 두 개의 광 검출기 대한 광 반응은 물질 특성들에 따라 가시광과 근적외선에서 각각 명확하게 나타났다. 이러한 결과들은 고속 에피택셜 리프트 오프 기법이 높은 픽셀 밀도 및 거의 완벽한 수직 정렬도를 갖는 한 기판상의 벌크 기반의 다중파장 광 검출기를 집적할 수 있다는 것을 의미한다. 미래의 목표하는 응용처에 따라, 원하는 파장들을 갖는 광 검출기를 벌크 구조로 간단하게 성장할 수 있고, 다중파장 이미징 시스템을 제작 할 수 있다.List of Figures i Chapter.1 Introduction 1 1.1 Photodetectors based on III-V compound semiconductors 1 1.2 Imaging applications 4 1.2.1. Single color imaing 4 1.2.2. Multicolor imaing 4 1.2.3. Development trend of photodetectors 5 1.3 Approches for forming multicolor photodectors 9 1.3.1. Epitaxy 9 1.3.2. Heterogeneous integration 17 1.3.3. Summary of each method 21 1.4 Overview of heterogeneous integration technology 23 1.4.1. Introduction 23 1.4.2. Direct bonding 24 1.4.3. Cold-weld bonding 26 1.4.4. Eutectic bonding 26 1.4.5. Adhesive bonding 28 1.4.7. Wafer splitting 31 1.4.8. Epitaxial lift off (ELO) 33 1.4.9. Benchmark of differenct heterogeneous intergration methods 35 1.5 Thesis overview 37 1.6 Bibliography 40 Chapter. 2 Method for heterogeneous integration of III-V compound semiconductors on other substrates 45 2.1 Introduction 45 2.1.1 The origin of low throughput in conventional ELO 46 2.1.2 Previous works for ehancement of ELO throughput 48 2.1.3 Approach: high-throughput ELO process 53 2.1.4 Experimental procedure 55 2.2 Results and discussion 57 2.3 Summary 65 2.4 Biblography 66 Chapter. 3 Verification of thin film devices by using a high throughput heterogeneous integration method 70 3.1 Introduction 70 3.2 Growth of device structures and heterogeneous integration 72 3.2.1. Device structures 72 3.2.2. Wafer bonding and ELO 74 3.3 Y2O3 bonded HEMTs on Si substrate 75 3.3.1 Fabrication process 75 3.3.2. Material characterization of HEMTs on Si 76 3.3.3. Electrical characterization of HEMTs on Si 80 3.3.4. Investigation of wafer reusability by using HEMT structure 83 3.4 Pt/Au bonded optoelectonic devices 86 3.4.1. Fabrication process of solar cells and HPTs on Si 86 3.4.2. Evaluation of Pt/Au metal bonding 88 3.4.3. Characterization of solar cells and HPTs 91 3.5 Estimation of production cost via recycling III-V wafers 95 3.6 Summary 101 3.7 Bibliography 102 Chapter. 4 Design and characterization of III-V based photodtectors 106 4.1 Introduction 106 4.1.1. The potential of Induim arsenide antimonide (InAsSb) 106 4.1.2. Challenges of InAsSb p-i-n PDs for compact detector systems 110 4.2 Barrier layer design and material characterization for growing HJPDs 113 4.2.1. Simulation of an optimum barrier layer for InAs0.8Sb0.2 113 4.2.2. Growth of a high quality InAsSb layer with an AlGaSb buffer layer grown on GaAs substrates 115 4.2.3. Ohmic contact formation with metal species 120 4.2.4. Growth and fabrication of InAsSb based HJPDs 126 4.3 Analysis of electrical and optical characteristics for fabricated PDs 129 4.4 Summary 138 4.5 Bibliography 139 Chapter. 5 Monolithic integration of visible/near-infrared photodetectors 145 5.1 Introduction 145 5.2 Fabrication process and material characterization of multicolor PD 148 5.3 Analysis of the electrical and optical characteristics of the fabricated multicolor PDs 154 5.4 Summary 163 5.5 Bibliography 164 Chapter. 6 Conclusions 169 국 문 초 록 172Docto

Soldering interconnects through self-propagating reaction process

This thesis presents a research into the solder interconnects made through the reactive bonding process based on the self-propagating reaction. A numerical study of soldering conditions in the heat affected zone (HAZ) during bonding was initially carried out in order to understand the self-propagating reactive bonding and the related influencing factors. This was subsequently followed by an extensive experimental work to evaluate the feasibility and reliability of the reactive bonding process to enable the optimisation of processing parameters, which had provided a detailed understanding in terms of interfacial characteristics and bonding strengths. In addition, by focusing on the microstructure of the bonds resulted from the self-propagating reactions, the interfacial reactions and microstructural evolution of the bonded structures and effects of high-temperature aging were studied in details and discussed accordingly. To study the soldering conditions, a 3D time-dependent model is established to describe the temperature and stress field induced during self-propagating reactions. The transient temperature and stress distribution at the critical locations are identified. This thus allows the prediction of the melting status of solder alloys and the stress concentration points (weak points) in the bond under certain soldering conditions, e.g. ambient temperature, pressure, dimension and type of solder materials. Experimentally, the characterisation of interconnects bonded using various materials under different technical conditions is carried out. This ultimately assists the understanding of the feasibility, reliability and failure modes of reactive bonding technique, as well as the criteria and optimisation to form robust joints. The formation of phases such as intermetallic compounds (IMCs) and mechanism of interfacial reactions during reactive bonding and subsequent aging are elaborated. The composition, dimension, distribution of phases have been examined through cross-sectional observations. The underlying temperature and stress profile determining the diffusion, crystallization and growth of phases are defined by numerical predictions. XXI Through the comparative analysis of the experimental and numerical results, the unique phases developed in the self-propagating joints are attributed to the solid-liquid-convective diffusion, directional solidification and non-equilibrium crystallization. The recrystallization and growth of phases during aging are revealed to be resulted from the solid-state diffusion and equilibration induced by the high-temperature heating. In conclusion, the interfacial reactions and microstructural evolution of interconnect developed through self-propagating reactive bonding are studied and correlated with the related influencing factors that has been obtained from these predictions and experiments. The results and findings enable the extensive uses of self-propagating reactive bonding technology for new design and assembly capable of various applications in electronic packaging. It also greatly contributes to the fundamentals of the crystallization and soldering mechanism of materials under the non-equilibrium conditions