Design and Characterization of Standard Cell Library using FinFETs

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor\u27s breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm node size is perceived to be the limit of scaling the CMOS transistors, but FinFETs can be scaled down further because of its unique design. Due to these advantages, the VLSI industry has now shifted to FinFET in implementation of their designs. However, these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in-depth understanding of them. This thesis explores the implementation of FinFETs using a standard cell library designed using these transistors. The FinFET package file used to design these cells is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design, the cells were characterized, the results were analyzed and compared with cells designed using CMOS transistors at different node sizes to understand and extrapolate conclusions on FinFET devices

Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, simulation, and physical layout are evaluated throughout the process. Modeling of the memory arrays for static timing analysis (STA) is done to allow easy integration of the design into a typical RTL design flow. System simulation data is incorporated into block-level simulations to validate the memory timing models. Hardware testing over five iterations of the memory array designs demonstrates the functionality of the design as well as validates the design specifications

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Challenges and Opportunities in Implementing Negative Differential Resistance Mode Reconfigurable Field Effect Transistors

Desirably, the world relies on the devices being compact, as they could drive to the increased functionality of integrated circuits at the provided footstep, that is becoming more reliable. To reduce the scalability over the devices, approach has been outlined utilizing the NDR mode reconfigurable functionality over the transistors. Being an individual device efficient in exhibiting different task with the different configurations in the same physical circuitry. On the view of reconfigurable transistors, possibly authorize the reconfiguration from a p-type to n-type channel transistor has been expelled as an emerging application such as static memory cells, fast switching logic circuits as well as energy efficient computational multi valued logic. This article emphasizes NDR mode RFET along with its classification, followed by enhancing the RFET technology concepts and RFETs future potential has been discussed briefing with the growing applications like hardware security as well as neuro-inspired computing.Comment: 28 pages, 9 figure

2D materials for Magnetic and Optoelectronic Sensing Applications

In the last decade, the emerging classes of two-dimensional (2D) materials have been studied as potential candidates for various sensing technologies, including magnetic and optoelectronic detectors. Within the quickly growing portfolio of 2D materials, graphene and semiconducting transition metal dichalcogenides (TMDs) have emerged as attractive candidates for various sensor applications because of their unique properties such as extreme thickness, excellent electrical and optical properties. In this thesis, I have exploited the unique properties of graphene and TMDs materials to develop 2D detectors based on field effect transistors for sensing magnetic field and light. In the first part of this thesis I have shown how the sensitivity of the properties of 2D materials to their surrounding environment can be turned into a feature useful to create new types of magnetic field sensors. The first experimental demonstration of this concept involved the use of graphene deposited on hexagonal Boron Nitride (h-BN), where the inevitable contaminations occurring at the interface of the two materials was used to generate a large magnetoresistance (MR) for a magnetic field sensor. Specifically, I have demonstrated that the contaminations generate an inhomogeneity in the carrier mobility throughout the channel, which is a required ingredient for magnetic field sensing based on linear magnetoresistance (LMR). Another approach I used to make a LMR sensor was by exploiting the large dependence of the mobility in graphene on the Fermi level position. This concept was used to generate two parallel electron gases with different mobility by tuning the Fermi level with an electrical field employing a field effect transistor. The second part of the thesis is focussed on strategies to reduce the impact of the surrounding environment on the properties of 2D materials in order to improve their performance. In particular, I used a 2D heterostructure encapsulated in an ionic polymer to makeii a highly responsive graphene-TMD photodetector. In this device, the ionic polymer covering the heterostructure was employed to screen the long-lived charge traps that limit the speed of such detectors, resulting in a drastic improvement of the detector responsivity properties. Finally, some of the 2D materials properties are very sensitive to the configuration of the electronics measurement setup. For example, effects behind spintronic and valleytronic concepts require non-local electrical transport measurement. We built a novel circuit that enables the detection of such effects without concern about the spurious contributions.The Higher Committee For Education Development in Iraq (HCED

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level