A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can be utilized successfully for bias currents as low as 1 nA, achieving sufficiently high gain (>3) over a wide frequency range

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product (EDP) figures. Multiple gates were simulated using 0.18µm standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts

Improving the power-delay performance in subthreshold source-coupled logic circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated

Pico-Watt Source-Coupled Logic Circuits

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18um CMOS technology, the bias current of each STSCL gate can be reduced below 10pA, which corresponds to a power-delay product (PDP) of less than 500aJ

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power-delay performance compared to their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to lower sensitivity to the process and supply voltage variations make STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The heart of such a system is a phase-locked loop (PLL)-based clock generator (CG) with a very wide tuning range controlling the dynamics of the STSCL system. The design of a wide tuning range PLL utilizing a novel self-adjustable loop filter that generates the reference clock as well as the bias current for the STSCL system is described. The PLL-based CG exhibits linear power-frequency characteristics in order to minimize its power consumption overhead (7 pJ with 350 nA standby current). Implemented in 0.13 μm CMOS, the CG occupies 0.06 mm2 with a supply voltage that can be reduced down to VDD = 0.9 V

Robustness Comparison of Emerging Devices for Portable Applications

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations

A Comparative Analysis of 6T and 10T SRAM Cells for Sub-threshold Operation in 65 nm CMOS Technology

The aggressive approach of the integrated electronics industry towards scaling and the growing trend of low-power applications have led to major research interest in ultra-low power integrated circuits. One of the integrated circuit areas most affected by this revolution is computer memory. In this thesis, a 10-Transistor Static Random Access Memory is compared to a 6-Transistor Static Random Access Memory in the subthreshold region of operation for a 65nm technology node. This comparison focuses primarily on the stability of memory cells in performing read and write operations. The use of 3-dimentional graphs in this thesis is to better compare differences and to give a feedback to memory designers about the design possibilities. A low-power Write Margin improvement method is proposed for the 10-Transistor cell to bring its stability to a standard comparable to that of its 6-transistor counterpart

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate contacts are used as gate- controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in sub-threshold CMOS circuits. Measurements in conventional 0.18um CMOS technology show that the tail bias current of each gate can be set as low as 10pA, with a supply voltage of 300mV. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized