7,363 research outputs found
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
Test exploration and validation using transaction level models
The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally wel
Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects
The tests of a complex system such as a microprocessor-based system-onchip
(SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis,
we propose three core-based test methods that reuse the existing functional
interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC),
and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism
(TAM). However, the use of functional interconnects as functional TAM's
introduces several new problems.
During tests, the interconnects-including the bus arbitrator, the bus bridges,
and the NoC routers-operate in the functional mode to transport the test stimuli
and responses, while the core under tests (CUT) operate in the test mode. Second,
the test data is transported to the CUT through the functional bus, and not
directly to the test port. Therefore, special core test wrappers that can provide
the necessary control signals required by the different functional interconnect are
proposed. We developed two types of wrappers, one buffer-based wrapper for the
bus-based systems and another pair of complementary wrappers for the NoCbased
systems.
Using the core test wrappers, we propose test scheduling schemes for the three
functionally different types of interconnects. The test scheduling scheme for a flat
bus is developed based on an efficient packet scheduling scheme that minimizes
both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of
the MPSoC systems. The third test scheduling scheme based on the bandwidth
sharing is developed specifically for the NoC-based systems. The test scheduling
is performed under the objective of co-optimizing the wrapper area cost and the
resulting test application time using the two complementary NoC wrappers.
For each of the proposed methodology for the three types of SoC architec ..
ture, we conducted a thorough experimental evaluation in order to verify their
effectiveness compared to other methods
Performance and Memory Space Optimizations for Embedded Systems
Embedded systems have three common principles: real-time performance, low power consumption, and low price (limited hardware). Embedded computers use chip multiprocessors (CMPs) to meet these expectations. However, one of the major problems is lack of efficient software support for CMPs; in particular, automated code parallelizers are needed.
The aim of this study is to explore various ways to increase performance, as well as reducing resource usage and energy consumption for embedded systems. We use code restructuring, loop scheduling, data transformation, code and data placement, and scratch-pad memory (SPM) management as our tools in different embedded system scenarios. The majority of our work is focused on loop scheduling. Main contributions of our work are:
We propose a memory saving strategy that exploits the value locality in array data by storing arrays in a compressed form. Based on the compressed forms of the input arrays, our approach automatically determines the compressed forms of the output arrays and also automatically restructures the code.
We propose and evaluate a compiler-directed code scheduling scheme, which considers both parallelism and data locality. It analyzes the code using a locality parallelism graph representation, and assigns the nodes of this graph to processors.We also introduce an Integer Linear Programming based formulation of the scheduling problem.
We propose a compiler-based SPM conscious loop scheduling strategy for array/loop based embedded applications. The method is to distribute loop iterations across parallel processors in an SPM-conscious manner. The compiler identifies potential SPM hits and misses, and distributes loop iterations such that the processors have close execution times.
We present an SPM management technique using Markov chain based data access.
We propose a compiler directed integrated code and data placement scheme for 2-D mesh based CMP architectures. Using a Code-Data Affinity Graph (CDAG) to represent the relationship between loop iterations and array data, it assigns the sets of loop iterations to processing cores and sets of data blocks to on-chip memories. We present a memory bank aware dynamic loop scheduling scheme for array intensive applications.The goal is to minimize the number of memory banks needed for executing the group of loop iterations
A Design Methodology for Space-Time Adapter
This paper presents a solution to efficiently explore the design space of
communication adapters. In most digital signal processing (DSP) applications,
the overall architecture of the system is significantly affected by
communication architecture, so the designers need specifically optimized
adapters. By explicitly modeling these communications within an effective
graph-theoretic model and analysis framework, we automatically generate an
optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs
a C description of Input/Output data scheduling, and user requirements
(throughput, latency, parallelism...), and formalizes communication constraints
through a Resource Constraints Graph (RCG). The RCG properties enable an
efficient architecture space exploration in order to synthesize a STAR
component. The proposed approach has been tested to design an industrial data
mixing block example: an Ultra-Wideband interleaver.Comment: ISBN : 978-1-59593-606-
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