On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Experiences on analog circuit technology migration and reuse

This work deals with two aspects of the reuse and redesign of analog circuits. First, a method for technology migration of analog circuits, recently proposed by Galup-Montoro and Schneider (Proc. SBCCI2000, pp. 89-93, 2000), is validated experimentally in the redesign of a Miller OTA from a 2.4 /spl mu/m technology to a 0.8 /spl mu/m technology. In addition, the impact of the method on performance aspects of analog circuits not covered in the original proposal (slew rate and current mirror frequency response) is studied. As a second mechanism for allowing the reuse of analog circuits, the feasibility of the application of the reference bias current as a tuning parameter to customize the performance of an existing design to suit different applications is demonstrate

Méthodologie de développement d'une bibliothèque d'IP-AMS en vue de la conception automatisée de systèmes sur puces analogiques et mixtes: application à l'ingénierie neuromorphique

Les travaux de cette thèse apportent une contribution à l'automatisation du flot de conception analogique et mixte, en termes de méthodologies de réutilisation. Des méthodologies de développement et d'exploration de bibliothèques d'IPs (Intellectual Property) analogiques sont développées : définition et caractérisation d'un IP analogique, création et exploration d'une base de données d'IPs, aide à la réutilisation destinée au concepteur. Le circuit utilisé pour l'application de ces méthodologies est un système neuromimétique c'est-à-dire qu'il reproduit l'activité électrique de neurones biologiques. Ces applications montrent à travers trois exemples, l'efficacité et la souplesse de notre méthodologie. Ces travaux proposent également une méthodologie de redimensionnement de circuits analogiques CMOS lors d'une migration technologique

Reusable Agena study. Volume 2: Technical

The application of the existing Agena vehicle as a reusable upper stage for the space shuttle is discussed. The primary objective of the study is to define those changes to the Agena required for it to function in the reusable mode in the 100 percent capture of the NASA-DOD mission model. This 100 percent capture is achieved without use of kick motors or stages by simply increasing the Agena propellant load by using optional strap-on-tanks. The required shuttle support equipment, launch and flight operations techniques, development program, and cost package are also defined

NASA Tech Briefs, Spring 1981

Topics include: NASA TU Services: Technology Utilization services that can assist you In learning about and applying NASA technology; New Product Ideas: A summary of selected innovations of value to manufacturers for the development of new products; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Life Sciences; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

NASA Tech Briefs Index 1980

Tech Briefs are short announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This Index to NASA Tech Briefs contains abstracts and four indexes -- subject,. personal author, originating Center, and Tech Brief number -- for 1980 Tech Briefs

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work