9 research outputs found
Symmetric rearrangeable networks and algorithms
A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature.
Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature.
As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks.
The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks
Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node
An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching
Blocking behaviors of crosstalk-free optical Banyan networks on vertical stacking
Banyan networks are attractive for constructing directional coupler (DC)-based optical switching networks for their small depth and self-routing capability. Crosstalk between optical signals passing through the same DC is an intrinsic drawback in DC-based optical networks. Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly. Though much work has been done for determining the minimum number of stacked copies (planes) required for a nonblocking VSOB network, little is known on analyzing the blocking probabilities of VSOB networks that do not meet the nonblocking condition (i.e., with fewer stacked copies than required by the nonblocking condition). In this paper, we analyze the blocking probabilities of VSOB networks and develop their upper and lower bounds with respect to the number of planes in the networks. These bounds depict accurately the overall blocking behaviors of VSOB networks and agree with the conditions of strictly nonblocking and rearrangeably nonblocking VSOB networks respectively. Extensive simulation on a network simulator with both random routing and packing strategy has shown that the blocking probabilities of both strategies fall nicely within our bounds, and the blocking probability of packing strategy actually matches the lower bound. The proposed bounds are significant because they reveal the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provide network developers a quantitative guidance to trade blocking probability for hardware cost. In particular, our bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied. An interesting conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible nonzero blocking probability is allowed.Xiaohong Jiang; Hong Shen; Khandker, Md.M.-ur-R.; Horiguchi, S
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Energy Efficient High Port Count Optical Switches
The advance of internet applications, such as video streaming, big data and cloud computing, is reshaping the telecommunication and internet industries. Bandwidth demands in datacentres have been boosted by these emerging data-hungry internet applications. Regarding inter- and intra-datacentre communications, fine-grained data need to be exchanged across a large shared memory space.
Large-scale high-speed optical switches tend to use a rearrangeably non-blocking architecture as this limits the number of switching elements required. However, this comes at the expense of requiring more sophisticated route selection within the switch and also some forms of time-slotted protocols. The looping algorithm is the classical routing algorithm to set up paths in rearrangeably non-blocking switches. It was born in the electronic switch era, where all links in the switches are equal. It is, therefore, not able to accommodate loss difference between optical paths due to the different length of waveguides and distinct numbers of crossings, and bends, leading to sub-optimal performance.
We, therefore, propose an advanced path-selection algorithm based on the looping algorithm that minimises the path-dependent loss. It explores all possible set-ups for a given connection assignment and selects the optimal one. It guarantees that no individual path would have a sufficiently substantial loss, therefore, improve the overall performance of the switch. The performance of the proposed algorithm has been assessed by modelling switches using the VPI simulator. An 8×8 Clos-tree switch demonstrates a 2.7dB decrease in loss and 1.9dB improvement in IPDR with 1.5 dB penalty for the worst case. An 8×8 dilated Beneš shows more than 4 dB loss reduction for the lossiest path and 1.4 dB IPDR improvement for 1 dB power penalty. The improved algorithm can be run once for each switch design and store its output in a compact lookup table, enabling rapid switch reconfiguration.
Microelectromechanical systems (MEMS) based optical switches have been fabricated with over 1,000 ports which meet the port count requirements in data centre networks. However, the reconfiguration speed of the MEMS switches is limited to the millisecond to microsecond timescale, which is not sufficient for packet switching in datacentres. Opto-electronic devices, such as Mach-Zehnder Interferometers (MZIs) and semiconductor optical amplifiers (SOAs) with nanosecond response time show the potential to fulfil the requirements of packet switching. However, the scalability of MZI switches is inherently limited by insertion loss and accumulated crosstalk, while the scalability of SOA switches is restricted by accumulated noise and distortion.
We, therefore, have proposed a dilated Beneš hybrid MZI-SOA design, where MZIs are implemented as 1×2 or 2×1 low-loss switching elements, minimising crosstalk by using a single input, and where short SOAs are included as gain or absorption units, offering either loss compensation or crosstalk suppression though adding only minimal noise and distortion. A 4×4 device has been fabricated and exhibits a mere 1.3dB loss, an extinction ratio of 47dB, and more than 13dB IPDR for a 0.5dB power penalty. When operating with 10 Gb/s per port, 6pJ/bit energy consumption is demonstrated, delivering 20% reduced energy consumption compared with SOA-based switches. The tolerance of the current control accuracy of this switch is very broad. Within a 5 mA bias current range, the power penalty can be maintained below 0.2 dB for 8 dB IPDR and 12 mA for 10 dB IPDR with a penalty less 0.5 dB. The excellent crosstalk and power penalty performance demonstrated by this chip enable the scalability of this hybrid approach. The performance of 16×16 port dilated Beneš hybrid switch is experimentally assessed by cascading 4×4 switch chips, demonstrating an IPDR of 15 dB at a 1 dB penalty with a 0.6 dB power penalty floor. In terms of switches with port count larger than 16×16, the power penalty performance has been analysed with physical layer simulations fitted with state-of-the-art data. We assess the feasibility of three potential topologies, with different architectural optimisations: dilated Beneš, Beneš and Clos-Beneš. Quantitative analysis for switches with up to 2048 ports is presented, achieving a 1.15dB penalty for a BER of 10-3, compatible with soft-decision forward error correction.Cambridge Overseas Trust; China Scholarship Council
ENVIRONMENTALLY FRIENDLY TECHNOLOGY: THE BEHAVIOUR OF NATURAL AND SYNTHETIC BINDER SYSTEMS WITHIN PAPER COATINGS
Coating shrinkage upon drying is a phenomenon well known to the paper coating industry, where it often causes
changes in the final structure of the coating layer leading to poor results in terms of gloss, light scattering, surface
strength, coverage, uniformity and printability. Such shrinkage has in previous studies been wrongly associated
with shrinkage of the polymeric binders used in the coating formulation, by making erroneous comparison with
solvent-based paint systems. Natural binders, as starch or proteins, which come from renewable resources and are
therefore environmentally friendly, suffer more from this shrinkage phenomenon than synthetic binders. The aim
of this research project was to improve the understanding of the processes involved in the drying of a coating
layer and to create a model able to describe them.
Shrinkage while the coating layer dries has been successfully measured by observing the deflection of coated
strips of a synthetic elastically-deformable substrate. Ground calcium carbonate was used as the coating pigment,
together with latex binders of both low and high glass transition temperature, Tg, respectively, and also with
starch which is a natural film-forming water soluble binder. The final dry coatings were studied with mercury
porosimetry and by scanning electron microscopy in order to characterise their porous structure. The flow and
rheological properties of the coating colour formulations were measured in order to probe the particle-particle
interaction between the different species in the wet coating colour.
The void space of the dry coating layers was modelled using Pore-Cor, a software which generates simulated
porous networks. A new algorithm was developed to model, within the simulated void space, the effective
particles or "skeletal elements" representative of the solid phase of the dried porous system. The water-filled
porous structures at the beginning of the shrinkage process (first critical concentration, FCC) were subsequently
modelled by creating Pore-Cor structures with the same solid skeletal elements distribution as at the second
critical concentration (at which the particles lock their positions), but with higher given porosity to account for
the water present The capillary forces acting on the surface of the simulated coating were calculated, and found
to be several orders of magnitude larger than the measured shrinkage forces. The shrinkage process was thus
described as resulting from the effect of capillary forces in the plane of the coating layer resisted by a stick-slip
process, where the capillary forces yield shrinkage only if a resistance force within the drying coating layer holds
the structure in place and allows the menisci to form. The stick-slip theory was strongly supported by quantitative
comparisons between the experimental forces required to intrude mercury, and the capillary forces within the
simulated void structure.Omya AG, Oftringen, Switzerlan
INTSORMIL 1999 Annual Report
Presently, worldwide, more than 800 million people do not get enough to eat or have access to a balanced diet to be healthy. At the World Food Summit in 1996, the United States of America (USA) and 185 other countries pledged to reduce the number of malnourished people by one half by 2015. It is shocking that about 33% of preschool children in developing countries will be stunted due to malnutrition by the year 2000. The number of stunted children in Africa alone has increased significantly from 35 million in 1980 to 45 million in 1995 and is predicted to reach 49 million in 2005. Increased production of cereals, which are crucial sources of food energy and other nutrients, is necessary to reduce world hunger.
Sorghum and millet are two major cereal grains, particularly in semi-arid regions. In 1999, 65.8 million tons ofsorghum were produced worldwide, of which 19.7 million tons were produced in Africa, mainly for direct consumption by humans, and 14.7 million tons were produced in the USA, mainly for livestock feed to produce meat for human consumption. In the crop year 1997-1998, the USA exported 5.3 million tons of grain sorghum mainly for livestock feed, and in 1998, U.S. grain sorghum exports were worth $531 million. Large areas are planted to sorghum each year. For example, in 1999, sorghum was produced on 44.8 million hectares (ha, or 173,036 square miles, [sq miD worldwide, 23 million ha (88,728 sq mi) in Africa, and 3.4 million ha (13,278 sqmi) in the USA. About 500 million people worldwide depend upon sorghum for food, and most of these people are in developing countries where droughts and famine are common occurrences. Clearly, sorghum production and its utilization as food and feed are vitally important to developing countries and to the USA