An online wear state monitoring methodology for off-the-shelf embedded processors

The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [13, 5] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this paper, we propose a lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither data on the threshold voltage and critical paths nor additional hardware. Our methodology can also be extended to predict the wear progression due to some other dominant IC failure mechanisms. Experiments on embedded processors provide insights on NBTI wear progression over time. This knowledge can be used to design real-time embedded systems that explicitly consider runtime wear progression to increase predictability and maintain lifetime reliability requirements

On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.

The VLSI industry has achieved advancement in technology by continuous process scaling which has resulted in large scale integration. However, scaling also poses new reliability challenges. Currently the industry ensures the reliability of chips by limiting the supply voltage and temperature, but these constraints limit the benefits that are obtained from new process nodes. This method of managing reliability during design time is called Static Reliability Management (SRM). While SRM ensures that all the chips meet the reliability specifications, it introduces extreme pessimism in the chips as it margins for worst process, voltage, temperature and circuit state (PVTS), which will not be required for the majority of chips. To reduce the pessimism of SRM, the system needs to be made aware of its reliability by employing degradation sensors or degradation detection techniques. Using the degradation measurements, the system can estimate its lifetime and can adjust its operating points (supply voltage and temperature limits) dynamically and trade excess reliability slack with performance. This method of reliability management is called Dynamic Reliability Management (DRM). In this work we investigate different methods of DRM. We focus on two critical degradation mechanisms: Negative Bias Temperature Instability (NBTI) and Gate-oxide degradation. We propose NBTI and Gate-oxide degradation sensors with low area and power overhead, which allows them to be deployed in large numbers on the chip enabling collection of degradation statistics. The sensors were designed in 130nm and 45nm process nodes and tested on two test-chips. We then used the sensors to perform DRM in a silicon test for the first time. We demonstrate that DRM eliminates excess reliability slack which allows for a boost in supply voltage and performance. We then propose in situ Bias Temperature Instability (BTI) and Gate-oxide wear-out detection techniques. The in situ technique measures the degradation in the actual devices in the core and removes all the layers of uncertainty which arise because of the statistical nature of degradation and its dependence on PVTS. We implemented and tested these techniques on two test chips in a 65nm process node. We then use the BTI sensing technique to perform DRM.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86281/1/prsingh_1.pd

Unreliable Silicon: Circuit through System-Level Techniques for Mitigating the Adverse Effects of Process Variation, Device Degradation and Environmental Conditions.

Designing and manufacturing integrated circuits in advanced, highly-scaled processing technologies that meet stringent specification sets is an increasingly unreliable proposition. Dimensional processing variations, time and stress dependent device degradation and potentially varying environmental conditions exacerbate deviations in performance, power and even functionality of integrated circuits. This work explores a system-level adaptive design philosophy intended to mitigate the power and performance impact of unreliable silicon devices and presents enabling circuits for SRAM variation mitigation and in-situ measurement of device degradation in 130nm and 45nm processing technologies. An adaptation of RAZOR-based DVS designed for on-chip memory power reduction and reliability lifetime improvement enables the elimination of 250 mV of voltage margin in a 1.8V design, with up to 500 mV of reduction when allowing 5% of memory operations to use multiple cycles. A novel PID-controlled dynamic reliability management (DRM) system is presented, allowing user-specified circuit lifetime to be dynamically managed via dynamic voltage and frequency scaling. Peak performance improvement of 20-35% is achievable in typical processing systems by allowing brief periods of elevated voltage operation through the real-time DRM system, while minimizing voltage during non-critical periods of operation to maximize circuit lifetime. A probabilistic analysis of oxide breakdown using the percolation model indicates the need for 1000-2000 integrated in-situ sensors to achieve oxide lifetime prediction error at or under 10%. The conclusions from the oxide analysis are used to guide the design of a series of novel on-chip reliability monitoring circuits for use in a real-time DRM system. A 130nm in-situ oxide breakdown measurement sensor presented is the first published design of an oxide-breakdown oriented circuit and is compatible with standard-cell style automatic “place and route” design styles used in the majority of application specific integrated circuit designs. Measured results show increases in gate oxide leakage of 14-35% after accelerated stress testing. A second generation design of the on-chip oxide degradation sensor is presented that reduces stress mode power consumption by 111,785X over the initial design while providing an ideal 1:1 mapping of gate leakage to output frequency in extracted simulations.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60701/1/ekarl_1.pd

Design and operation of automated ice-tethered profilers for real-time seawater observations in the polar oceans

An automated, easily-deployed Ice-Tethered Profiler (ITP) has been developed for deployment on perennial sea ice in polar oceans to measure changes in upper ocean temperature and salinity in all seasons. The ITP system consists of three components: a surface instrument that sits atop an ice floe, a weighted, plastic-jacketed wire-rope tether of arbitrary length (up to 800 m) suspended from the surface instrument, and an instrumented underwater unit that profiles up and down the wire tether. The profiling underwater unit is similar in shape and dimension to an ARGO float except that the float's variable-buoyancy system is replaced with a traction drive unit. Deployment of ITPs may be conducted either from ice caps or icebreakers, utilizing a self contained tripod/winch system that requires no power. Careful selection of an appropriate multiyear ice floe is needed to prolong the lifetime of the system (up to 3 years depending on the profiling schedule). Shortly after deployment, each ITP begins profiling the water column at its programmed sampling interval. After each acquired temperature and salinity profile, the underwater unit (PROCON) transfers the data and engineering files using an inductive modem to the surface controller (SURFCON). SURFCON also accumulates battery voltages, buoy temperature, and locations from GPS at specified intervals in status files, and queues that information for transmission at the start of each new day. At frequent intervals, an Iridium satellite transceiver in the surface package calls and transmits queued status and CTD data files onto a WHOI logger computer, which are subsequently processed and displayed in near-real time at http://www.whoi.edu/itp. In 2004 and 2005, three ITP prototypes were deployed in the Arctic Ocean. Each system was programmed with accelerated sampling schedules of multiple one-way traverses per day between 10 and 750-760 m depth in order to quickly evaluate endurance and component fatigue. Two of the ITPs are continuing to function after more than 10 months and 1200 profiles. Larger motor currents are observed at times of fast ice floe motion when larger wire angles develop and drag forces on the profiler are increased. The CTD profile data so far obtained document interesting spatial variations in the major water masses of the Beaufort Gyre, show the double-diffusive thermohaline staircase that lies above the warm, salty Atlantic layer, and many mesoscale eddys. Deployed together with CRREL Ice Mass Balance (IMB) buoys, these ITP systems also operate as part of an Ice Based Observatory (IBO). Data returned from an array of IBOs within an Arctic Observing Network will provide valuable real time observations, support studies of ocean processes, and facilitate numerical model initialization and validation.Funding was provided by the National Science Foundation under Contract Nos. OCE-0324233 and ARC-0519899

Integrated Circuit Wear-out Prediction and Recycling Detection using Radio-Frequency Distinct Native Attribute Features

Radio Frequency Distinct Native Attribute (RF-DNA) has shown promise for detecting differences in Integrated Circuits(IC) using features extracted from a devices Unintentional Radio Emissions (URE). This ability of RF-DNA relies upon process variation imparted to a semiconductor device during manufacturing. However, internal components in modern ICs electronically age and wear out over their operational lifetime. RF-DNA techniques are adopted from prior work and applied to MSP430 URE to address the following research goals: 1) Does device wear-out impact RF-DNA device discriminability?, 2) Can device age be continuously estimated by monitoring changes in RF-DNA features?, and 3) Can device age state (e.g., new vs. used) be reliably estimated? Conclusions include: 1) device wear-out does impact RF-DNA, with up to a 16 change in discriminability over the range of accelerated ages considered, 2) continuous(hour-by-hour) age estimation was most challenging and generally not supported, and 3) binary new vs. used age estimation was successful with 78.7 to 99.9 average discriminability for all device-age combinations considered