The VLSI industry has achieved advancement in technology by continuous process
scaling which has resulted in large scale integration. However, scaling also poses new
reliability challenges. Currently the industry ensures the reliability of chips by limiting
the supply voltage and temperature, but these constraints limit the benefits that are
obtained from new process nodes. This method of managing reliability during design
time is called Static Reliability Management (SRM). While SRM ensures that all the
chips meet the reliability specifications, it introduces extreme pessimism in the chips as it
margins for worst process, voltage, temperature and circuit state (PVTS), which will not
be required for the majority of chips. To reduce the pessimism of SRM, the system needs
to be made aware of its reliability by employing degradation sensors or degradation
detection techniques. Using the degradation measurements, the system can estimate its
lifetime and can adjust its operating points (supply voltage and temperature limits)
dynamically and trade excess reliability slack with performance. This method of
reliability management is called Dynamic Reliability Management (DRM).
In this work we investigate different methods of DRM. We focus on two critical
degradation mechanisms: Negative Bias Temperature Instability (NBTI) and Gate-oxide
degradation. We propose NBTI and Gate-oxide degradation sensors with low area and
power overhead, which allows them to be deployed in large numbers on the chip enabling
collection of degradation statistics. The sensors were designed in 130nm and 45nm
process nodes and tested on two test-chips. We then used the sensors to perform DRM in
a silicon test for the first time. We demonstrate that DRM eliminates excess reliability
slack which allows for a boost in supply voltage and performance.
We then propose in situ Bias Temperature Instability (BTI) and Gate-oxide wear-out
detection techniques. The in situ technique measures the degradation in the actual devices
in the core and removes all the layers of uncertainty which arise because of the statistical
nature of degradation and its dependence on PVTS. We implemented and tested these
techniques on two test chips in a 65nm process node. We then use the BTI sensing
technique to perform DRM.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86281/1/prsingh_1.pd
