Thermal Stress Analysis of Liquid-Cooled 3D-ICs

It is known that 3D-ICs suffer from hot spot temperatures that can reach thousands of degrees, if they are not cooled to reasonable operating temperatures. The problem of hot spots is not limited to the high temperatures of the IC; thermal stress can also pose severe problems, even after cooling the chip. This study investigates thermal stress resulting from a 3D-IC hot spot with 20 W power dissipation. The IC is cooled using SiO2 and diamond cooling blocks. The study is performed using three cooling liquids: water, Freon (R22), and Liquid Nitrogen (LN). As expected, the study shows that metal layers on the chip suffer from high thermal stress due to rising the chip temperature to values higher than the room temperature. It is also noticed that the stress becomes more severe, if cooling is done using LN. In fact, the stress exceeded the maximum tensile strength of aluminum, which means failure of the chip. This indicates that cooling 3D-IC may not ensure acceptable operation or reliability. Thermal stress must be investigated at both high and low temperatures to ensure high performance and acceptable reliability.Comment: This article has been accepted for presentation in the IEEE-EIT 2020 conference. The article is 4 pages and 11 Figure

Harnessing heterogeneous nucleation to control tin orientations in electronic interconnections

While many aspects of electronics manufacturing are controlled with great precision, the nucleation of tin in solder joints is currently left to chance. This leads to a widely varying melt undercooling and different crystal orientations in each joint which results in a different resistance to electromigration, thermomechanical fatigue and other failure modes in each joint. Here we identify a family of nucleants for tin, prove their effectiveness using a novel droplet solidification technique, and demonstrate an approach to incorporate the nucleants into solder joints to control the orientation of the tin nucleation event. With this approach, it is possible to change tin nucleation from a stochastic to a deterministic process, and to generate single crystal joints with their c-axis orientation tailored to best combat a selected failure mode

Carbon nanotubes on graphene: Electrical and interfacial properties

An integrated circuit (IC) consists of copper (Cu) and tungsten (W) interconnects to facilitate conduction among its components such as transistors, resistors, and capacitors. As the minimum feature size in IC technology continues to scale downward into the sub-20 nm regime, interconnects are faced with performance and reliability challenges arising from increased resistance and electromigration, respectively [1]. To partially mitigate such challenges, our project aims at studying a structure as a potential replacement for Cu and W, formed by growing carbon nanotubes (CNTs) directly onto graphene, and investigating the resulting electrical and interfacial properties. Various CNT/Graphene structures are fabricated using sputtered iron (Fe), cobalt (Co), or nickel (Ni) catalyst films and subsequent thermal chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes for CNT growth. The objective of this research is to assess the viability of CNTs directly grown on graphene as a functional alternative to Cu and W interconnects in integrated circuits. Using Co as a catalyst for CNT growth with a thermal CVD process, we have succeeded in creating a conductive all-carbon 3D interconnect structure

Effects of stress and electromigration on microstructural evolution in microbumps of three-dimensional integrated circuits

Due to geometric scaling, the heterogeneous and anisotropic microstructures present in through-silicon vias and microbumps must be considered in the stress management of 3-D integrated circuits. In this paper, a phase field model is developed to investigate the effects of stress and electromigration on microstructural evolution in a Cu/Sn-microbump/Cu structure at 150 °C. External compressive stress is observed to accelerate the growth of Cu3Sn grains and cause the separation of continuous interfacial Cu 6 Sn 5 grains by β-Sn grains, whereas tensile stress promotes the growth of Cu 6 Sn 5 grains and the formation of a continuous Cu 6 Sn 5 layer. The roughness of the β-Sn-Cu 6 Sn 5 interface under compressive stress is greater than that under tensile stress. The morphological evolution of the β-Sn grains is also affected by stress. An external shear or compressive stress favors the growth of the β-Sn grains with their c-axis particular to the Y -direction. Furthermore, the interdiffusion flux driven by electromigration increases the roughness of the interfacial Cu 6 Sn 5 grains at the cathode. The strain caused by electromigration results in larger β-Sn grains, enabling faster interdiffusion along the current direction. The preferential growth of the β-Sn grains under stress or electromigration decreases the shear modulus of microbumps

On the Interfacial Phase Growth and Vacancy Evolution during Accelerated Electromigration in Cu/Sn/Cu Microjoints

In this work, we integrate different computational tools based on multi-phase-field simulations to account for the evolution of morphologies and crystallographic defects of Cu/Sn/Cu sandwich interconnect structures that are widely used in three dimensional integrated circuits (3DICs). Specifically, this work accounts for diffusion-driven formation and disappearance of multiple intermetallic phases during accelerated electromigration and takes into account the non-equilibrium formation of vacancies due to electromigration. The work compares nucleation, growth, and coalescence of intermetallic layers during transient liquid phase bonding and virtual joint structure evolution subjected to accelerated electromigration conditions at different temperatures. The changes in the rate of dissolution of Cu from intermetallics and the differences in the evolution of intermetallic layers depending on whether they act as cathodes or anodes are accounted for and are compared favorably with experiments. The model considers non-equilibrium evolution of vacancies that form due to differences in couplings between diffusing atoms and electron flows. This work is significant as the point defect evolution in 3DIC solder joints during electromigration has deep implications to the formation and coalescence of voids that ultimately compromise the structural and functional integrity of the joints.NSF Grant No.CMMI-146225

The effects of grain structure on electromigration failure of the lead-free solder bump

This paper carries out an electromigration (EM) acceleration test on ball grid array (BGA) samples with Sn96.5/Ag3.0/Cu0.5 solder bumps under constant temperature, and characterizes the structure of β-Sn grains in the lead-free solder bumps. The EM failure modes of the solder bumps of different grain structures were analysed, aiming to disclose the effect of grain structure on the EM failure. Considering the driving forces of the EM (i.e. electron wind force, stress gradient, temperature gradient and atomic density gradient), the atomic density integral (ADI) method was introduced to simulate the void formation and failure lifetime of the EM. The simulation results show that solder bump reliability and failure mode are greatly affected by grain orientation, in that the EM failure occurs rapidly when the c-axis of grain structure of the solder bump is strongly misaligned, or almost perpendicular, to the current direction. The double grain solder bump with grain boundary parallel to current direction boasts a small EM failure and thus a long lifetime

Effects of underfill material on solder deformation and damage in 3D packages

This paper will examine the effects of the introduction of a periodic boundary condition and the presence of underfill material on the stress and strain fields and evolution of failure of an FEA model that is representative of a solder joint in a 3D IC package. The model solder joint is placed between two silicon substrates in contact with through-silicon vias without any other devices or components attached. Differing solder joint thicknesses, both with and without underfill, will be examined to study the effect on the stress and strain fields as well as the evolution of failure in the solder joint. A dynamic loading on the FEA model will be used to examine the fracture pattern and mode of failure when the solder thickness is varied both with and without underfill material present