Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Strain Engineering for Advanced Silicon Transistors

Ph.DDOCTOR OF PHILOSOPH

Elastic strain engineering for unprecedented materials properties

“Smaller is stronger.” Nanostructured materials such as thin films, nanowires, nanoparticles, bulk nanocomposites, and atomic sheets can withstand non-hydrostatic (e.g., tensile or shear) stresses up to a significant fraction of their ideal strength without inelastic relaxation by plasticity or fracture. Large elastic strains, up to ∼10%, can be generated by epitaxy or by external loading on small-volume or bulk-scale nanomaterials and can be spatially homogeneous or inhomogeneous. This leads to new possibilities for tuning the physical and chemical properties of a material, such as electronic, optical, magnetic, phononic, and catalytic properties, by varying the six-dimensional elastic strain as continuous variables. By controlling the elastic strain field statically or dynamically, a much larger parameter space opens up for optimizing the functional properties of materials, which gives new meaning to Richard Feynman’s 1959 statement, “there’s plenty of room at the bottom.”National Science Foundation (U.S.) (DMR-1240933)National Science Foundation (U.S.) (DMR-1120901

Strain Engineering for Advanced Silicon, Germanium and Germanium-Tin Transistors

Ph.DDOCTOR OF PHILOSOPH

Device Design Parameterization of III-V Multi-Gate FETs

The use of group III-V semiconductor materials promise superior performance compared to silicon and can be considered a fundamental paradigm shift away from mature silicon technology. Group III-V semiconductors allow for high power operation, drastically high clock speeds, large breakdown fields, and higher Johnson’s Figure of Merit (JFoM). Due to higher electron drift velocity (vd) of the material set, higher on-state current (Ion) is expected than the one in silicon with reduced supply voltage operation. Additionally, strong spontaneous and piezoelectric polarization properties in the III-Nitrides support tighter carrier confinement with high carrier density in a quantum well channel at the heterointerface. By engineering the III-nitride properties, designing a 3D architecture device includes important physical parameters that must be taken into account to analyze device performance. GaN-based devices are desirable for high RF and high power applications for reducing parasitics and improving efficiency. For this reason, III-nitride semiconductor materials provide the possibility of future integration of GaN fin-based 3D devices. This dissertation describes the experimental realization and electrical analysis of III-V FinFET devices with an AlGaN/GaN heterostructure, called “Multi-Gate Heterostructure Fin Field Effect Transistor (MUG-HFinFET).” Process development begins with the experimental demonstration of a Si-compatible baseline AlGaN/GaN FinFET technology, and an exploration of the impact of physical device design parameters such as fin widths, heights, angles and gate lengths. The ohmic contact formation on AlGaN/GaN heterostructure is realized using different metal stacks while taking into account additional annealing effects and produces comparably low contact resistance to other literature reports. Different fabrication processes to distinguish the impact of the device architectures are demonstrated while simultaneously applying for the integration of high-k dielectric metal-gate stack including surface clean and passivation techniques developed for high quality interfaces and low-leakage performance. After MUG-HFinFET technology is implemented and characterized, the impacts of the device design parameters are benchmarked and shows the guidance to device design at the initial stage forward proper device application. The work concludes by assessing the novel characteristics of AlGaN/GaN heterostructure FinFET devices for 3D device design with distinguished performance. According to the distinguished performance across the device geometries and crystal directions, the benchmarks made in this dissertation will guide future device application development toward an AlGaN/GaN FinFET device design to ensure that a proper device design is achieved

Fabrication, characterization, and modeling of silicon multi-gate devices

Ph.DDOCTOR OF PHILOSOPH

Multi-gate Si nanowire MOSFETs:fabrication, strain engineering and transport analysis

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of such archi- tectures due to higher electrostatic control of the channel. On the other hand, Si nanowires show excellent mechanical properties e.g. yield and fracture strengths of 10±2% and 30±1% in comparison to 3.7% and 4.0% for bulk Si, respectively, a strong motivation to be used as exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or lo- cal band-gap modulation using > 4 GPa uniaxial tensile stress in suspended Si channels to enhance the band-to-band tunneling current in multi-gate Tunnel-FETs, all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels. In this thesis and as a first step, a precise built-in stress analysis during local thermal oxidation of suspended Si NWs in the presence of a Si3N4 tensile hard mask was done. Accumulation of up to 2.6 GPa uniaxial tensile stress in the buckled NWs is reported. The contribution of hard mask/spacer engineering on the stress level and the NW formation was studied and buckled self-aligned dual NW MOSFETs on bulk Si with two sub-100 nm cross-sectional Si cores including ∼0.8 uniaxial tensile stress are reported. Micro-Raman spectroscopy was widely used in this thesis to measure stress in the buckled NWs on both bulk and SOI substrates. A process flow was designed to make dense array of GAA sub-5 nm cross-sectional Si NWs using a SOI substrate including a high level of stress. The NW stress level can be engineered simply using e.g. metal-gate thin film stress suitable for both NMOS and PMOS devices. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless and accumulation-mode devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in order to fabricate shorter channel length devices. Therefore, in this process flow, a highly doped accumulation-mode was targeted as the operation mechanism. Finally, extensive TCAD device simulation was done on GAA Si NW JL MOSFETs to study the corner effects on the device characteristics, from subthreshold to strong accumulation, report the concept of local volume accumulation/depletion, quantum flat-band voltage, significant bias-dependent series resistance in junctionless MOSFETs and finally, support the experimental data to extract precisely the carrier mobility in sub-5 nm Si NW MOSFETs

Advanced Silicon and Germanium Transistors for Future P-channel MOSFET Applications

Ph.DDOCTOR OF PHILOSOPH

Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry