Flight Dynamics Operations of the TanDEM-X Formation

Since end of 2010 the German TerraSAR-X and TanDEM-X satellites are routinely operated as the first configurable single-pass Synthetic Aperture Radar interferometer in space. The two 1340 kg satellites fly in a 514 km sun-synchronous orbit. In order to collect sufficient measurements for the generation of a global digital elevation model and to demonstrate new interferometric SAR techniques and applications, more than three years of formation flying are foreseen with flexible baselines ranging from 150 m to few kilometers. As a prerequisite for the close formation flight an extensive flight dynamics system was established at DLR/GSOC, which comprises of GPS-based absolute and relative navigation and impulsive orbit and formation control. Daily formation maintenance maneuvers are performed by TanDEM-X to counterbalance natural and artificial disturbances. The paper elaborates on the routine flight dynamics operations and its interactions with mission planning and ground-station network. The navigation and formation control concepts and the achieved control accuracy are briefly outlined. Furthermore, the paper addresses non-routine operations experienced during formation acquisition, frequent formation reconfiguration, formation maintenance problems and space debris collision avoidance, which is even more challenging than for single-satellite operations. In particular two close approaches of debris are presented, which were experienced in March 2011 and April 2012. Finally, a formation break-up procedure is discussed which could be executed in case of severe onboard failures

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications. The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The CGRAs are ASICs and therefore, expensive to produce. However, Field Programmable Gate Arrays (FPGAs) are relatively cheaper for low volume products but they are not so easily programmable. We combine best of both worlds by implementing a Virtual Coarse-Grained Reconfigurable Array (VCGRA) on FPGA. VCGRAs are a trade off between FPGA with large routing overheads and ASICs. In this perspective we present a novel heterogeneous Virtual Coarse-Grained Reconfigurable Array (VCGRA) called "Pixie" which is suitable for implementing high performance image processing applications. The proposed VCGRA contains generic processing elements and virtual channels that are described using the Hardware Description Language VHDL. Both elements have been optimized by using the parameterized configuration tool flow and result in a resource reduction of 24% for each processing elements and 82% for each virtual channels respectively.Comment: Presented at 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017) arXiv:1704.0880

Shift factor-based SCOPF topology control MIP formulations with substation configurations

Topology control (TC) is an effective tool for managing congestion, contingency events, and overload control. The majority of TC research has focused on line and transformer switching. Substation reconfiguration is an additional TC action, which consists of opening or closing breakers not in series with lines or transformers. Some reconfiguration actions can be simpler to implement than branch opening, seen as a less invasive action. This paper introduces two formulations that incorporate substation reconfiguration with branch opening in a unified TC framework. The first method starts from a topology with all candidate breakers open, and breaker closing is emulated and optimized using virtual transactions. The second method takes the opposite approach, starting from a fully closed topology and optimizing breaker openings. We provide a theoretical framework for both methods and formulate security-constrained shift factor MIP TC formulations that incorporate both breaker and branch switching. By maintaining the shift factor formulation, we take advantage of its compactness, especially in the context of contingency constraints, and by focusing on reconfiguring substations, we hope to provide system operators additional flexibility in their TC decision processes. Simulation results on a subarea of PJM illustrate the application of the two formulations to realistic systems.The work was supported in part by the Advanced Research Projects Agency-Energy, U.S. Department of Energy, under Grant DE-AR0000223 and in part by the U.S. National Science Foundation Emerging Frontiers in Research and Innovation under Grant 1038230. Paper no. TPWRS-01497-2015. (DE-AR0000223 - Advanced Research Projects Agency-Energy, U.S. Department of Energy; 1038230 - U.S. National Science Foundation Emerging Frontiers in Research and Innovation)http://buprimo.hosted.exlibrisgroup.com/primo_library/libweb/action/openurl?date=2017&issue=2&isSerivcesPage=true&spage=1179&dscnt=2&url_ctx_fmt=null&vid=BU&volume=32&institution=bosu&issn=0885-8950&id=doi:10.1109/TPWRS.2016.2574324&dstmp=1522778516872&fromLogin=truePublished versio

Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation

Optimal load shedding for microgrids with unlimited DGs

Recent years, increasing trends on electrical supply demand, make us to search for the new alternative in supplying the electrical power. A study in micro grid system with embedded Distribution Generations (DGs) to the system is rapidly increasing. Micro grid system basically is design either operate in islanding mode or interconnect with the main grid system. In any condition, the system must have reliable power supply and operating at low transmission power loss. During the emergency state such as outages of power due to electrical or mechanical faults in the system, it is important for the system to shed any load in order to maintain the system stability and security. In order to reduce the transmission loss, it is very important to calculate best size of the DGs as well as to find the best positions in locating the DG itself.. Analytical Hierarchy Process (AHP) has been applied to find and calculate the load shedding priorities based on decision alternatives which have been made. The main objective of this project is to optimize the load shedding in the micro grid system with unlimited DG’s by applied optimization technique Gravitational Search Algorithm (GSA). The technique is used to optimize the placement and sizing of DGs, as well as to optimal the load shedding. Several load shedding schemes have been proposed and studied in this project such as load shedding with fixed priority index, without priority index and with dynamic priority index. The proposed technique was tested on the IEEE 69 Test Bus Distribution system

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints