10 research outputs found

    Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

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    The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times. On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime

    Demonstrating effective all-optical processing in ultrafast data networks using semiconductor optical amplifiers

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references.The demand for bandwidth in worldwide data networks continues to increase due to growing Internet use and high-bandwidth applications such as video. All-optical signal processing is one promising technique for providing the necessary capacity and offers payload transparency, power consumption which scales efficiently with increasing bit rates, reduced processing latency, and ultrafast performance. In this thesis, we focus on using semiconductor optical amplifier-based logic gates to address both routing and regeneration needs in ultrafast data networks. To address routing needs, we demonstrate a scalable, multi-packet all-optical header processing unit operating at a line rate of 40 Gb/s. For this experiment, we used the ultrafast nonlinear interferometer (UNI) gate, a discrete optical logic gate which has been demonstrated at speeds of 100 Gb/s for bit-wise switching. However, for all-optical switching to become a reality, integration is necessary to significantly reduce the cost of manufacturing, installation, and operation. One promising integrated all-optical logic gate is the semiconductor optical amplifier Mach-Zehnder interferometer (SOA-MZI). This gate has previously been demonstrated capable of up to 80 Gb/s bit-wise switching operation. To enable simple installation and operation of this gate, we developed a performance optimization method which can quickly and accurately pinpoint the optimal operating point of the switch. This eliminates the need for a time-intensive search over a large parameter space and significantly simplifies the operation of the switch. With this method, we demonstrate the ability of a single SOA-MZI logic gate to regenerate ultrafast pulses over 100 passes and 10,000 km in a regenerative loop. Ultimately, all-optical logic gates must be integrated on a single low-cost platform and demonstrated in cascaded, multi-gate operation for increased functionality.(cont.) This requires low-loss monolithic integration. Our approach to this involves an asymmetric twin waveguide (ATG) design. This design also has the potential for high-yields as a result of a high tolerance for fabrication errors. We present our characterization results of ATG waveguides and proposals for future improvements.by Jade P. Wang.Ph.D

    Optical flow switched networks

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Includes bibliographical references (p. 253-279).In the four decades since optical fiber was introduced as a communications medium, optical networking has revolutionized the telecommunications landscape. It has enabled the Internet as we know it today, and is central to the realization of Network-Centric Warfare in the defense world. Sustained exponential growth in communications bandwidth demand, however, is requiring that the nexus of innovation in optical networking continue, in order to ensure cost-effective communications in the future. In this thesis, we present Optical Flow Switching (OFS) as a key enabler of scalable future optical networks. The general idea behind OFS-agile, end-to-end, all-optical connections-is decades old, if not as old as the field of optical networking itself. However, owing to the absence of an application for it, OFS remained an underdeveloped idea-bereft of how it could be implemented, how well it would perform, and how much it would cost relative to other architectures. The contributions of this thesis are in providing partial answers to these three broad questions. With respect to implementation, we address the physical layer design of OFS in the metro-area and access, and develop sensible scheduling algorithms for OFS communication. Our performance study comprises a comparative capacity analysis for the wide-area, as well as an analytical approximation of the throughput-delay tradeoff offered by OFS for inter-MAN communication. Lastly, with regard to the economics of OFS, we employ an approximate capital expenditure model, which enables a throughput-cost comparison of OFS with other prominent candidate architectures. Our conclusions point to the fact that OFS offers significant advantage over other architectures in economic scalability.(cont.) In particular, for sufficiently heavy traffic, OFS handles large transactions at far lower cost than other optical network architectures. In light of the increasing importance of large transactions in both commercial and defense networks, we conclude that OFS may be crucial to the future viability of optical networking.by Guy E. Weichenberg.Ph.D

    Small Business Innovation Research. Program solicitation. Closing date: July 21, 1992

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    The National Aeronautics and Space Administration (NASA) invites small businesses to submit Phase 1 proposals in response to its Small Business Innovation Research (SBIR) Program Solicitation 92-1. Firms with research or research and development capabilities (R/R&D) in science or engineering in any of the areas listed are encouraged to participate. This, the tenth annual SBIR solicitation by NASA, describes the program, identifies eligibility requirements, describes the proposal evaluation and award selection process, and provides other information to assist those interested in participating in NASA's SBIR program. It also identifies, in Section 8.0, the technical topics and subtopics in which SBIR Phase 1 proposals are solicited in 1992. These topics and subtopics cover a broad range of current NASA interests but do not necessarily include all areas in which NASA plans or currently conducts research. The NASA SBIR program seeks innovative approaches that respond to the needs, technical requirements, and new opportunities described in the subtopics. The focus is on innovation through the use of emerging technologies, novel applications of existing technologies, exploitation of scientific breakthroughs, or new capabilities or major improvements to existing technologies. NASA plans to select about 320 high-quality research or research and development proposals for Phase 1 contract awards on the basis of this Solicitation. Phase 1 contracts are normally six months in duration and funded up to $50,000, including profit. Selections will be based on the competitive merits of the offers and on NASA needs and priorities

    Topical Workshop on Electronics for Particle Physics

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    The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

    Cumulative index to NASA Tech Briefs, 1970-1975

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    Tech briefs of technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Abstracts and indexes of subject, personal author, originating center, and tech brief number for the 1970-1975 tech briefs are presented
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