Reconfigurable Asynchronous Logic Automata (RALA)

Computer science has served to insulate programs and programmers from knowledge of the underlying mechanisms used to manipulate information, however this fiction is increasingly hard to maintain as computing devices decrease in size and systems increase in complexity. Manifestations of these limits appearing in computers include scaling issues in interconnect, dissipation, and coding. Reconfigurable Asynchronous Logic Automata (RALA) is an alternative formulation of computation that seeks to align logical and physical descriptions by exposing rather than hiding this underlying reality. Instead of physical units being represented in computer programs only as abstract symbols, RALA is based on a lattice of cells that asynchronously pass state tokens corresponding to physical resources. We introduce the design of RALA, review its relationships to its many progenitors, and discuss its benefits, implementation, programming, and extensions.National Science Foundation (U.S.) Center for Bits and AtomsUnited States. Army Research Office (Grant number W911NF-08-1-0254)United States. Army Research Office (Grant number W911NF-09-1-0542

Wireless Mesh Networks for Small Satellites Subsystems

Wireless mesh networks are a network topology where all the nodes of a system are able to communicate with every other node in the network. This enables an adaptable network that is scalable and has the capability to self-repair and self-configure. The Modular Rapidly Manufactured Small Sat (MRMSS) Project is a small satellite project where we are developing a modular CubeSat architecture. One of the goals of the project is to develop a system that is quick and simple to integrate with a minimal amount of wiring involved. Wireless mesh networks are well suited for this configuration because of the self- configuring and self-repairing aspects of the network. This enables a satellite developer to add subsystem nodes to the network without the need for much hardware re-design. This paper will detail the background of wireless mesh networks, the advantages and limitations of using wireless mesh networks for space applications, and the technical progress of the wireless mesh network development of the MRMSS project

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Logic matter : digital logic as heuristics for physical self-guided-assembly

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Architecture; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 123-124).Given the increasing complexity of the physical structures surrounding our everyday environment -- buildings, machines, computers and almost every other physical object that humans interact with -- the processes of assembling these complex structures are inevitably caught in a battle of time, complexity and human/machine processing power. If we are to keep up with this exponential growth in construction complexity we need to develop automated assembly logic embedded within our material parts to aid in construction. In this thesis I introduce Logic Matter as a system of passive mechanical digital logic modules for self-guided-assembly of large-scale structures. As opposed to current systems in self-reconfigurable robotics, Logic Matter introduces scalability, robustness, redundancy and local heuristics to achieve passive assembly. I propose a mechanical module that implements digital NAND logic as an effective tool for encoding local and global assembly sequences. I then show a physical prototype that successfully demonstrates the described mechanics, encoded information and passive self-guided-assembly. Finally, I show exciting potentials of Logic Matter as a new system of computing with applications in space/volume filling, surface construction, and 3D circuit assembly.by Skylar J.E. Tibbits.S.M

Programmable surfaces

Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 131-135).Robotic vehicles walk on legs, roll on wheels, are pulled by tracks, pushed by propellers, lifted by wings, and steered by rudders. All of these systems share the common character of momentum transport across their surfaces. These existing approaches rely on bulk response among the fluids and solids. They are often not finely controllable and complex approaches suffer from manufacturing and practical operational challenges. In contrast I present a study of a dynamic, programmable interface between the surface and its surrounding fluids. This research explores a synthetic hydrodynamic regime, using a programmable surface to dynamically alter the flow around an object. Recent advances in distributed computing and communications, actuator integration and batch fabrication, make it feasible to create intelligent active surfaces, with significant implications for improving energy efficiency, recovering energy, introducing novel form factors and control laws, and reducing noise signatures. My approach applies ideas from programmable matter to surfaces rather than volumes. The project is based on covering surfaces with large arrays of small cells that can each compute, communicate, and generate shear or normal forces. The basic element is a cell that can be joined in arrays to tile a surface, each containing a processor, connections for power and communications, and means to control the local wall velocity The cell size is determined by the characteristic length scale of the flow field ranging from millimeters to centimeters to match the desired motion and fluidic system. Because boundary layer effects are significant across fluid states from aerodynamics to hydrodynamics to rheology, the possible implications of active control of the boundary layer are correspondingly far reaching, with applications from transportation to energy generation to building air handling. This thesis presents a feasibility study, evaluating current manufacturing, processing, materials, and technologies capabilities to realize programmable surfaces.by Amy Sun.Ph.D

Asynchronous techniques for new generation variation-tolerant FPGA

PhD ThesisThis thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the design’s margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLB’s overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lion’s share of the modern FPGA’s soft fabric, and yet permits the dual-rail iv completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method

Dynamically reconfigurable asynchronous processor

The main design requirements for today's mobile applications are: · high throughput performance. · high energy efficiency. · high programmability. Until now, the choice of platform has often been limited to Application-Specific Integrated Circuits (ASICs), due to their best-of-breed performance and power consumption. The economies of scale possible with these high-volume markets have traditionally been able to hide the high Non-Recurring Engineering (NRE) costs required for designing and fabricating new ASICs. However, with the NREs and design time escalating with each generation of mobile applications, this practice may be reaching its limit. Designers today are looking at programmable solutions, so that they can respond more rapidly to changes in the market and spread costs over several generations of mobile applications. However, there have been few feasible alternatives to ASICs: Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much area and power. Coarse-grained dynamically reconfigurable architectures offer better solutions for high throughput applications, when power and area considerations are taken into account. One promising example is the Reconfigurable Instruction Cell Array (RICA). RICA consists of an array of cells with an interconnect that can be dynamically reconfigured on every cycle. This allows quite complex datapaths to be rendered onto the fabric and executed in a single configuration - making these architectures particularly suitable to stream processing. Furthermore, RICA can be programmed from C, making it a good fit with existing design methodologies. However the RICA architecture has a drawback: poor scalability in terms of area and power. As the core gets bigger, the number of sequential elements in the array must be increased significantly to maintain the ability to achieve high throughputs through pipelining. As a result, a larger clock tree is required to synchronise the increased number of sequential elements. The clock tree therefore takes up a larger percentage of the area and power consumption of the core. This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor (DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA architecture, but uses asynchronous design techniques - methods of designing digital systems without clocks. The absence of a global clock signal makes DRAP more scalable in terms of power and area overhead than its synchronous counterpart. The DRAP architecture maintains most of the benefits of custom asynchronous design, whilst also providing programmability via conventional high-level languages. Results show that the DRAP processor delivers considerably lower power consumption when compared to a market-leading Very Long Instruction Word (VLIW) processor and a low-power ARM processor. For example, DRAP resulted in a reduction in power consumption of 20 times compared to the ARM7 processor, and 29 times compared to the TIC64x VLIW, when running the same benchmark capped to the same throughput and for the same process technology (0.13μm). When compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but resulted in a power reduction of up to 1.9 times. It was also capable of achieving up to 2.8 times higher throughputs than RICA for the same benchmarks

自律電源電圧制御に基づく低消費電力リコンフィギャラブルVLSI アーキテクチャに関する研究

Tohoku University亀山充隆課