Improving the Steering Efficiency of 1x4096 Opto-VLSI Processor using Direct Power Measurement Method

We report optimization of the steering efficiency of the 1-D Opto-VLSI processor using direct power measurement method for wavelengths in the near-IR and 632 nm. Highest improvement observed for the signal and interport isolation is 8 dB and 12 dB respectively. This improved performance of the processor is crucial to the realization of low crosstalk reconfigurable optical add/drop multiplexers (ROADM) using Opto-VLSI processors

Opto-VLSI processing for reconfigurable optical devices

The implementation of Wavelength Division Multiplexing system (WDM) optical fibre transmission systems has the potential to realise this high capacity data rate exceeding 10 Tb/s. The ability to reconfigure optical networks is a desirable attribute for future metro applications where light paths can be set up or taken down dynamically as required in the network. The use of microelectronics in conjunction with photonics enables intelligence to be added to the high-speed capability of photonics, thus realising reconfigurable optical devices which can revolutionise optical telecommunications and many more application areas. In this thesis, we investigate and demonstrate the capability of Opto-VLSI processors to realise a reconfigurable WDM optical device of many functions, namely, optical multiband filtering, optical notch filtering, and reconfigurable-Optical-Add-Drop Multiplexing (ROADM). We review the potential technologies available for tunable WDM components, and discuss their advantages and disadvantages. We also develop a simple yet effective algorithm that optimises the performance of Opto-VLSI processors, and demonstrate experimentally the multi-function WDM devices employing Opto-VLSI processors. Finally, the feasibility of Opto-VLSI-based WDM devices in meeting the stringent requirements of the optical communications industry is discussed

CMOS Vision Sensors: Embedding Computer Vision at Imaging Front-Ends

CMOS Image Sensors (CIS) are key for imaging technol-ogies. These chips are conceived for capturing opticalscenes focused on their surface, and for delivering elec-trical images, commonly in digital format. CISs may incor-porate intelligence; however, their smartness basicallyconcerns calibration, error correction and other similartasks. The term CVISs (CMOS VIsion Sensors) definesother class of sensor front-ends which are aimed at per-forming vision tasks right at the focal plane. They havebeen running under names such as computational imagesensors, vision sensors and silicon retinas, among others. CVIS and CISs are similar regarding physical imple-mentation. However, while inputs of both CIS and CVISare images captured by photo-sensors placed at thefocal-plane, CVISs primary outputs may not be imagesbut either image features or even decisions based on thespatial-temporal analysis of the scenes. We may hencestate that CVISs are more “intelligent” than CISs as theyfocus on information instead of on raw data. Actually,CVIS architectures capable of extracting and interpretingthe information contained in images, and prompting reac-tion commands thereof, have been explored for years inacademia, and industrial applications are recently ramp-ing up.One of the challenges of CVISs architects is incorporat-ing computer vision concepts into the design flow. Theendeavor is ambitious because imaging and computervision communities are rather disjoint groups talking dif-ferent languages. The Cellular Nonlinear Network Univer-sal Machine (CNNUM) paradigm, proposed by Profs.Chua and Roska, defined an adequate framework forsuch conciliation as it is particularly well suited for hard-ware-software co-design [1]-[4]. This paper overviewsCVISs chips that were conceived and prototyped at IMSEVision Lab over the past twenty years. Some of them fitthe CNNUM paradigm while others are tangential to it. Allthem employ per-pixel mixed-signal processing circuitryto achieve sensor-processing concurrency in the quest offast operation with reduced energy budget.Junta de Andalucía TIC 2012-2338Ministerio de Economía y Competitividad TEC 2015-66878-C3-1-R y TEC 2015-66878-C3-3-

Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm

With ubiquitous wireless communication via Wi-Fi and nascent 5th Generation mobile communications, more devices -- both smart and traditionally dumb -- will be interconnected than ever before. This burgeoning trend is referred to as the Internet-of-Things. These new sensing opportunities place a larger burden on the underlying circuitry that must operate on finite battery power and/or within energy-constrained environments. New developments of low-power reconfigurable analog sensing platforms like field-programmable analog arrays (FPAAs) present an attractive sensing solution by processing data in the analog domain while staying flexible in design. This work addresses some of the contemporary challenges of low-power wireless sensing via traditional application-specific sensing and with FPAAs. A large emphasis is placed on furthering the development of FPAAs by making them more accessible to designers without a strong integrated-circuit background -- much like FPGAs have done for digital designers

Demonstration of Tunable Optical Notch Filter Using 1-D Opto-VLSI Processor

An opto-very-large-scale-integrated (opto-VLSI)-based tunable optical filter structure is demonstrated. Filter tunability is achieved by reconfiguring the holographic diffraction grating of an opto-VLSI processor, allowing virtually any type of filter response to be synthesized. A proof-of-concept tunable notch filter with wavelength span of 7 nm is experimentally verifie

Linear-cavity tunable fibre lasers employing an Opto-VLSI processor and a MEMS-based device

This thesis proposes and demonstrates experimentally two novel linear-cavity tunable fibre lasers employing an erbium-doped fibre (EDF) in conjunction with an Opto- VLSI processor and a MEMS-based device for wavelength selection. The Opto-VLSI processor and the MEMS-based device along with an optical collimator, a Bragg grating plate and an optical lens, enable the realisation of an optical filter for continuous tuning of wavelengths over the amplified spontaneous emission (ASE) range of the EDF. We also propose the use of a section of un-pumped EDF as a saturable absorber (SA), which suppresses noise spikes caused by the high optical pumping power. Experimental results show that by optimising a length of the SA a single wavelength, high power laser signal can be achieved. In addition, we experimentally demonstrate that the performance of the proposed linear-cavity tunable fibre lasers is better than that of ring-cavity tunable laser counterparts. Specifically, we show that linear-cavity based tunable fibre lasers can achieve higher output power, a larger side mode rejection ratio (SMRR) and narrower laser linewidth than ring-cavity tunable fibre lasers

Opto-VLSI-based adaptive optical power splitter/combiner for next generation dynamic optical telecommunication networks

The demand for optical power splitters is growing globally, due to the rapid deployment of fibre-to-the-premises, optical metropolitan area network (MAN), and active optical cables for TV/Video signal transport. Optical splitters play an important role in passive optical network (PON) technology by enabling several hundred users to share one optical line terminal. However, current PONs, which use fixed optical power splitters, have limited reconfigurability particularly in adding/dropping users to/from an optical network unit. An adaptive optical power splitter (OPS) can dynamically reallocate the opticalpower in the entire network according to the real-time distribution of users and services, thus providing numerous advantages such as improve an optical network efficiency, scalability, and reliability. An adaptive OPS is also important for realizing self-healing ring-to-ring optical MAN, thus offering automatic communication recovery when line break occurs. In addition, future optical line protection systems will require adaptive optical splitters to switch optical signals from faulty lines to active power lines, avoid the use of optical attenuators and/or amplifiers, and achieve real time line monitoring. An adaptive OPS can also be incorporated in tunable optical dispersion compensators, optical attenuator and optical gain equalizer, and reconfigurable optical switches. This thesis proposes and demonstrates the principle of a novel Opto-VLSI-based adaptive optical splitter/combiner for next generation dynamic optical telecommunication networks. The proposed splitter structure enables an input optical power to be split adaptively into a larger number of output fibre ports, through optimized phase holograms driving the Opto-VLSI processor. The new adaptive optical splitter has additional advantages including lossless operation, adequate inter-port crosstalk, compressed hardware and simple user interface. This thesis demonstrates, in particular, the concept of an adaptive optical power splitter employing an Opto-VLSI processor and a 4-f imaging system experimentally in three stages as follow: (i) a 1×2 adaptive optical power splitter based on an Opto-VLSI processor, a fibre collimator array and 4-f imaging systems (single lens), (ii) a 1×4 adaptive optical power splitter based on an Opto-VLSI processor, a fibre array and 4-f imaging systems (single lens), and (iii) a 1×N lossless adaptive optical power splitter structure integrating an Opto-VLSI processor, optical amplifiers, a fibre array, and an array of 4-f imaging systems (lens array). The thesis also demonstrates the concept of an adaptive optical signal combiner which enables multiple signals to be combined with user-defined weight profiles into a single fibre port. Experimental results demonstrate that an input optical signal can arbitrarily be split into N signals and coupled into optical fibre ports by uploading optimized multicasting phase holograms onto the Opto-VLSI processor. They also demonstrate that N input optical signals can be dynamically combined with arbitrary weights into a single optical fibre port. Excellent agreement between theoretical and experimental results is demonstrated. The total insertion loss of the optical power splitter is only 5 dB. Results also show that the optical amplifiers can compensate for the insertion and splitting losses, thus enabling lossless splitter operation. A crosstalk level around -25 dB and a wavelength spectral range exceeding 40 nm is experimentally realized. In addition, a novel broadband adaptive RF power splitter/combiner based on Opto-VLSI processor is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, the input RF signal is dynamically split and directed to different output ports, with userdefined splitting ratios. Also, multiple input RF signals can be dynamically combined with arbitrary user-defined weights. As a proof-of-concept demonstration, two input RF signals are dynamically combined with different user-defined weight profiles. We also propose and demonstrate a photonic microwave filter based on the use of an Opto-VLSI-based adaptive optical combiner. The experimental results demonstrate that the developed Opto-VLSI-based adaptive optical combiner can dynamically route multiple input optical signals to a single output, with user-defined weight profiles, thus realising a tunable microwave filter. Overall this Opto-VLSI-based adaptive optical power splitter should allow as many as 32 output ports to be supported while achieving high splitting resolution and dynamic range. This will greatly enhance the efficiency of optical communication networks

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

Rewriting History: Repurposing Domain-Specific CGRAs

Coarse-grained reconfigurable arrays (CGRAs) are domain-specific devices promising both the flexibility of FPGAs and the performance of ASICs. However, with restricted domains comes a danger: designing chips that cannot accelerate enough current and future software to justify the hardware cost. We introduce FlexC, the first flexible CGRA compiler, which allows CGRAs to be adapted to operations they do not natively support. FlexC uses dataflow rewriting, replacing unsupported regions of code with equivalent operations that are supported by the CGRA. We use equality saturation, a technique enabling efficient exploration of a large space of rewrite rules, to effectively search through the program-space for supported programs. We applied FlexC to over 2,000 loop kernels, compiling to four different research CGRAs and 300 generated CGRAs and demonstrate a 2.2$\times$ increase in the number of loop kernels accelerated leading to 3$\times$ speedup compared to an Arm A5 CPU on kernels that would otherwise be unsupported by the accelerator