Temperature Regulation in Multicore Processors Using Adjustable-Gain Integral Controllers

This paper considers the problem of temperature regulation in multicore processors by dynamic voltage-frequency scaling. We propose a feedback law that is based on an integral controller with adjustable gain, designed for fast tracking convergence in the face of model uncertainties, time-varying plants, and tight computing-timing constraints. Moreover, unlike prior works we consider a nonlinear, time-varying plant model that trades off precision for simple and efficient on-line computations. Cycle-level, full system simulator implementation and evaluation illustrates fast and accurate tracking of given temperature reference values, and compares favorably with fixed-gain controllers.Comment: 8 pages, 6 figures, IEEE Conference on Control Applications 2015, Accepted Versio

Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range. Our data suggest that, for application processors operating between 20{\deg}C and 50{\deg}C, a quadratic model is still accurate and a linear approximation is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV

Self-Aware Thermal Management for High-Performance Computing Processors

Editor's note: Thermal management in high-performance multicore platforms has become exceedingly complex due to variable workloads, thermal heterogeneity, and long, thermal transients. This article addresses these complexities by sophisticated analysis of noisy thermal sensor readings, dynamic learning to adapt to the peculiarities of the hardware and the applications, and a dynamic optimization strategy. - Axel Jantsch, TU Wien - Nikil Dutt, University of California at Irvine

Energy-Efficient Thermal-Aware Scheduling for RT Tasks Using TCPN

This work leverages TCPNs to design an energy-efficient, thermal-aware real-time scheduler for a multiprocessor system that normally runs in a low state energy at maximum system utilization but its capable of increasing the clock frequency to serve aperiodic tasks, optimizing energy, and honoring temporal and thermal constraints. An off-line stage computes the minimum frequency required to run the periodic tasks at maximum CPU utilization, the proportion of each task''s job to be run on each CPU, the maximum clock frequency that keeps temperature under a limit, and the available cycles (slack) with respect to the system with minimum frequency. Then, a Zero-Laxity online scheduler dispatches the periodic tasks according to the offline calculation. Upon the arrival of aperiodic tasks, it increases clock frequency in such a way that all periodic and aperiodic tasks are properly executed. Thermal and temporal requirements are always guaranteed, and energy consumption is minimized

Thermal/performance trade-off in network-on-chip architectures

Multi-core architectures are a promising paradigm to exploit the huge integration density reached by high-performance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM technique

Thermal-aware real-time scheduling using timed continuous Petri Nets

We present a thermal-aware, hard real-time (HRT) global scheduler for a multiprocessor system designed upon three novel techinques. First, we present a modeling methodology based on Timed Continuous Petri nets (TCPN) that yields a complete state variable model, including job arrivals, CPU usage, power, and thermal behavior. The model is accurate and avoids the calibration stage of RC thermal models. Second, based on this model, a linear programming problem (LPP) determines the existence of a feasible HRT thermal-aware schedule. Last, a sliding-mode controller and an online discretization algorithm implement the global HRT scheduler, which is capable of managing thermal constraints, context switching, migrations, and disturbances

Data Mining for Thermal Analysis of Big Dataset of HPC-Data Center

Greening of Data Centers could be achieved through energy savings in two major areas namely: compute systems and cooling systems. A reliable cooling system is necessary to produce a persistent flow of cold air to cool the servers due to increasingly demanding computational load. Servers’ dissipated heat effects a strain on the cooling systems. Consequently, it is imperative to individual servers that frequently occur in the hotspot zones. This is facilitated through the application of data mining techniques to an available big data set with thermal characteristics of HPC-ENEA-Data Center, namely Cresco 6. This work involves the implementation of an advanced algorithm on the workload management platform produces hotspots maps with the goal to reduce data centre wide thermal-gradient, and cooling effectiveness

Exploratory data analysis for data center energy management

The continuous improvement in energy efficiency of existing data centers would help reduce their environmental footprints. Greening of Data Centers could be attained using renewable energy sources or more energy efficient compute systems and effective cooling systems. A reliable cooling system is necessary to generate a persistent flow of cold air to cool servers that are subjected to increasing computational load demand. As a matter of fact, servers' dissipated heat effects a strain on the cooling systems and consequently, on electricity consumption. Generated heat in the data center is categorized into different granularity levels namely: server level, rack level, room level, and data center level. Several datasets are collected at ENEA Portici Data Center from CRESCO 6 cluster-A High-Performance Computing Cluster. The cooling and environmental aspects of the data center is also considered for data analysis. This research aims to conduct a rigorous exploratory data analysis on each dataset separately and collectively followed in various stages. This work presents descriptive and inferential analyses for feature selection and extraction process. Furthermore, a supervised Machine learning modelling and correlation estimation is performed on all the datasets to abstract relevant features.That would have an impact on energy efficiency in data centers

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast