Model order reduction techniques for PEEC modeling of RF & high-speed multi-layer circuits.

by Hu Hai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.Includes bibliographical references.Abstracts in English and Chinese.Author's Declaration --- p.iiAbstract --- p.iiiAcknowledgements --- p.viTable of Contents --- p.viiiList of Figures --- p.xiList of Tables --- p.xivChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Overview of This Work --- p.2Chapter 1.3 --- Original Contributions in the Thesis --- p.3Chapter 1.4 --- Thesis Organization --- p.4Chapter Chapter 2 --- PEEC Modeling Background --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- PEEC Principles --- p.6Chapter 2.3 --- Meshing Scheme --- p.10Chapter 2.4 --- Formulae for Calculating the Partial Elements --- p.12Chapter 2.4.1 --- Partial Inductance --- p.12Chapter 2.4.2 --- Partial Capacitance --- p.14Chapter 2.5 --- PEEC Application Example --- p.15Chapter 2.6 --- Summary --- p.17References --- p.18Chapter Chapter 3 --- Mathematical Model Order Reduction --- p.20Chapter 3.1 --- Introduction --- p.20Chapter 3.2 --- Modified Nodal Analysis --- p.21Chapter 3.2.1 --- Standard Nodal Analysis Method Review --- p.22Chapter 3.2.2 --- General Theory of Modified Nodal Analysis --- p.23Chapter 3.2.3 --- Calculate the System Poles Using MNA --- p.27Chapter 3.2.4 --- Examples and Comparisons --- p.28Chapter 3.3 --- Krylov Subspace MOR Method --- p.30Chapter 3.4 --- Examples of Krylov Subspace MOR --- p.32Chapter 3.5 --- Summary --- p.34References --- p.35Chapter Chapter 4 --- Physical Model Order Reduction --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Gaussian Elimination Method --- p.39Chapter 4.3 --- A Lossy PEEC Circuit Model --- p.44Chapter 4.3.1 --- Loss with Capacitance --- p.44Chapter 4.3.2 --- Loss with Inductance --- p.46Chapter 4.4 --- Conversion of Mutual Inductive Couplings --- p.47Chapter 4.5 --- Model Order Reduction Schemes --- p.50Chapter 4.5.1 --- Taylor Expansion Based MOR Scheme (Type I) --- p.51Chapter 4.5.2 --- Derived Complex-valued MOR Scheme (Type II) --- p.65Chapter 4.6 --- Summary --- p.88References --- p.88Chapter Chapter 5 --- Concluding Remarks --- p.92Chapter 5.1 --- Conclusion --- p.92Chapter 5.2 --- Future Improvement --- p.93Author's Publication --- p.9

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Mobile array designs with ANSERLIN antennas and efficient, wide-band PEEC models for interconnect and power distribution network analysis

A mobile, wide-band antenna system has been developed around the ANSERLIN antenna element and a 3-dB splitter design. The size of the antenna elements was reduced over previous versions by introducing dielectric substrates. Additionally, new variations of the antenna were designed to influence radiation characteristics. To further reduce the number of components in the array, a very low profile splitter was designed and mounted below one of the antenna elements, doubling as the return plane for the antenna. The partial-element equivalent circuit (PEEC) method has been used for 3D interconnect analysis and numerous other applications. Being based on the same ideas as the method of moments, the PEEC method generates dense matrices for its cell interactions. This thesis contains research focused on efficiently using a limited number of cells for accurate results. This has been approached with a hybrid method and also with grid refinements. Additionally, the accuracy of PEEC coupling over electrically long distances has been addressed using wide-band accurate partial parameter calculations --Abstract, page iii

Beyond Moore's technologies: operation principles of a superconductor alternative

The predictions of Moore's law are considered by experts to be valid until 2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore's alternative for the development of supercomputers. In this paper, we consider operation principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined.Comment: OPEN ACCES

Characterization and modeling of microwave spiral inductors and transformers

Ph.DDOCTOR OF PHILOSOPH

Multi-resonant passive components for power conversion

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 199-202).Semiconductor-device limitations to system miniaturization have receded, but exposed by their improvement numerous "ancillary" barriers which continue to preoccupy nearly every electronics industry. Prominent among these obstacles are package parasitics and heat, which have come to the fore as conventional circuits are applied in modern regimes of frequency and integration density. To an ever increasing extent, integration limits are symptoms of the fundamental frequency- and size-scaling limits of passive components. Power inductors and transformers, in particular, are challenging to miniaturize because of their poor performance when scaled down in size, and the difficulty of fabricating them with available planar processes. A family of approximating networks for transmission lines, the focus of this work, enables miniaturization by internally circulating energy and exchanging delay fidelity for bulk energy storage. These multi-resonant components are substantially smaller than their lumped counterparts, in particular requiring less inductance, and enforce useful waveform symmetries that can be traded for higher power or higher efficiency.Lumped analogs of transmission lines, and delay-based means of processing energy in general, exploit rather than fight the parasitics which can restrict conventional designs to lower switching frequencies, and are compatible with RF power-conversion techniques. Printed-circuit and wafer- or package-scale construction methods for multi-resonant structures are presented, along with power-converter topologies that exploit the waveform symmetries they enforce. A new soft-switched RF power converter is introduced, in particular, that demonstrates reductions in peak device stress and passive-component size. Taken together, the construction techniques, networks, and converter topologies presented here extend the power levels and applications for which passive components can be manufactured in an integrated fashion, within a printed circuit board or at the die/package scale alongside semiconductor switches and converter controls.by Joshua W. Phinney.Ph.D

Design of miniaturized radio-frequency DC-DC power converters

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 321-325).Power electronics appear in nearly every piece of modern electronic hardware, forming an essential conduit from electrical source to load. Portable electronics, an area where a premium is placed on size, weight, and cost, are driving the development of power systems with greater density and better manufacturability. This motivates a push to higher switching frequencies enabling smaller passive components and better integration. To realize these goals this thesis explores devices, circuits, and passives capable of operating efficiently into the VHF regime (30-300 MHz) and their integration into power electronic systems of high power density. A good integrated power MOSFET presages high-density converters. Previous VHF systems were demonstrated with bulky and expensive RF Lateral, Double-Diffused MOSFETs (LDMOSFET). We show that through a combination of layout optimization and safe operating area (SOA) extension integrated devices can achieve near-parity performance to their purpose-built RF discrete cousins over the desired operating regime. A layout optimization method demonstrating a 2x reduction in device loss is presented alongside experimental demonstration of SOA extension. Together the methods yield a 3x reduction in loss that bolsters the utility of the typical (and relatively inexpensive) LDMOS IC power process for VHF converters. Passive component synthesis is addressed in the context of an isolated VHF converter topology. We present a VHF topology where most of the magnetic energy storage is accomplished in a transformer that forms an essential part of the resonant network. The reduced component count aids in manufacturability and size, but places difficult requirements on the transformer design. An algorithm for synthesizing small and efficient air-core transformers with a fully-constrained inductance matrix is presented. Planar PCB transformers are fabricated and match the the design specifications to within 15%. They are 94% efficient and have a power density greater than 2kW per cubic inch. To take full advantage of good devices and printed passives, we develop an IC for the isolated converter having optimized power devices, and integrated gate driver, controller, and hotel functions. The chip is assembled into a complete converter system using the transformers and circuits described above. Flip-chip mounting is used to overcome bondwire parasitics, and reduce packaging volume. The final system achieves 75% efficiency at 75 MHz at 6W.by Anthony D. Sagneri.Ph.D