A Novel Thread Scheduler Design for Polymorphic Embedded Systems

A novel thread scheduler design for polymorphic embedded systems Abstract: The ever-increasing complexity of current day embedded systems necessitates that these systems be adaptable and scalable to user demands. With the growing use of consumer electronic devices, embedded computing is steadily approaching the desktop computing trend. End users expect their consumer electronic devices to operate faster than before and offer support for a wide range of applications. In order to accommodate a broad range of user applications, the challenge is to come up with an efficient design for the embedded system scheduler. Hence the primary goal of the thesis is to design a thread scheduler for a polymorphic thread computing embedded system. This is the first ever novel attempt at designing a polymorphic thread scheduler as none of the existing or conventional schedulers have accounted for thread polymorphism. To summarize the thesis work, a dynamic thread scheduler for a Multiple Application, Multithreaded polymorphic system has been implemented with User satisfaction as its objective function. The sigmoid function helps to accurately model end user perception in an embedded system as opposed to the conventional systems where the objective is to maximize/minimize the performance metric such as performance, power, energy etc. The Polymorphic thread scheduler framework which operates in a dynamic environment with N multithreaded applications has been explained and evaluated. Randomly generated Application graphs are used to test the Polymorphic scheduler framework. The benefits obtained by using User Satisfaction as the objective function and the performance enhancements obtained using the novel thread scheduler are demonstrated clearly using the result graphs. The advantages of the proposed greedy thread scheduling algorithm are demonstrated by comparison against conventional thread scheduling approaches like First Come First Serve (FCFS) and priority scheduling schemes

Software support for dynamic partial reconfigurable FPGAs on heterogeneous platforms

This thesis addresses the design and implementation of a software support for real-time systems developed on heterogeneous platforms that include a processor and an FPGA with dynamic partial reconfiguration capabilities. The software support enables tasks to request the execution of accelerated functions on the FPGA in parallel with other tasks running on the processor. Accelerated functions are dynamically allocated on the FPGA depending of the availability of the area and the online requests issued by the processor, so extending the concept of multitasking to the FPGA resource domain. The performance of the allocation mechanism has been evaluated in terms of speed-up and response times. The achieved results show that the system is able to guarantee bounded delays and acceptable overhead that can be taken into account for a future schedulability analysis of real-time applications

Eğitim amaçlı yapılandırılabilir modüler donanım üzerine gömülü işletim sistemi tasarımı

06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Eski bir çin atasözünde “Dinlersem unuturum, görürsem hatırlarım, uygularsam anlarım” veciz ifadesinden de anlaşılacağı üzere, bir konu hakkında en ideal öğrenmenin, öğrenilen teorik bilgilerin uygulamaya geçirilmesinden geçmektedir. Elektronik Mühendisliği, Bilgisayar Mühendisliği ve buna benzer bilim dallarında önemli bir yer teşkil eden Bilgisayar Mimarisi ve Organizasyonu ile İşletim Sistemi derslerinde teorik olarak işlenen kavramların pratiğe dönüştürülmesi günümüz eğitim sisteminin problemleri arasında yer almaktadır. Gelişen teknoloji ile beraber bu derslerin uygulama ihtiyacını karşılamaya yönelik yazılımsal ve donanımsal temelli çözümler üretilmiştir. İşletim Sistemleri dersine yönelik yapılan eğitimsel çalışmalar Bilgisayar Mimarisi ve Organizasyonu dersine yönelik yapılan çalışmalar ile karşılaştırıldığında özgün sistem tasarlama motivasyonu açısından yetersiz olduğu görülmektedir. Bu çözüm adımlarına son yıllarda alanda programlanabilir kapı dizileri(FPGA- Field Programmable Gate Arrays) geliştirme ortamları kullanılarak yeni bir yaklaşım getirilmeye çalışılmıştır. Bu geliştirme ortamları kullanılarak geliştirilen eğitimsel çalışmalar simülasyon ortamındaki ideal şartların yerine gerçek dünya şartları altında gözlenebilen, çalıştırılabilen, elle tutulabilen yapıların ortaya çıkmasına neden olmuştur. Bu tez kapsamında yapılan ilk çalışma 2009 yılında tasarladığımız yazılımsal tabanlı bilgisayar mimarisine modüler özellik katılarak FPGA geliştirme ortamına aktarılmıştır. Modülerlik özelliği kullanıcılara sisteme müdahil olma avantajını getirerek özellikle Bilgisayar Mimarisi ve Organizasyonu dersine yönelik motivasyon artıcı bir etki getirmiştir. Başka bir deyişle kullanıcı sistemdeki bir bileşenin yerine kendi tasarımını ekleyerek sistemin işleyişinde herhangi bir olumsuzluğa neden olmaması kullanıcının bu derse karşı motivasyonunu artıran kullanıcı dostu bir özelliktir. Bu nedenle kullanıcı büyük bir sistemin karmaşası içinde kaybolmadan sistemdeki birimleri kullanıcı tabanlı tasarımlarla değiştirerek kendi bilgisayar mimarisini oluşturabilecektir. Ayrıca modüler özellikli donanımsal tabanlı bilgisayar mimarisi üzerine sıfırdan bir işletim sisteminin nasıl tasarlanacağı konusunda eğitimsel bir doküman hazırlanarak literatürde bu alanda bir kullanıcı rehberi olması hedeflenmiştir. Tasarlanan işletim sistemi bilgisayar mimarisinin sahip olduğu assembly dili ile yazılan özgün bir işletim sistemi olup eğitimsel amaçlı olarak literatürde kullanılmak üzere yer alacaktır.An old Chinese proverb says “I hear, and I forget; I see, and I remember; I do, and I understand”. As is understood from this expression, the most ideal learning about a topic is to put into practice the theoretical knowledge learned. Computer Organization and Operating Systems courses play a significant role in the Electronics Engineering, Computer Engineering and similar disciplines. To convert practice the concepts handled in these courses are among the problems of today’s education system. It has been produced hardware and software based solutions to eliminate the need for application in these courses using technology. The educational tools prepared for operating systems course is insufficient in terms of the motivation of original system design compared with computer organization and architecture course In addition to these solutions, it has been brought new approach using FPGA(Field Programmable Gate Array) development environments. The educational tools solution developed by using FPGA development environments brought about observable, executable and tangible structures under real world conditions instead of the ideal conditions in the simulation environment. The computer architecture developed using an emulator program that we designed in 2009 is embedded to the FPGA development board by including the modular approach in this thesis. The modular approach allowed the effect for enhancing motivation to users by bringing involving feature in especially computer architecture and organization course. In other words, it is user friendly that since the user defined design does not cause any negative effect at the process of system and to be able to integrate their designs instead of a component of the system. In this way, the user will obtain the own computer architecture by changing the related system’s components with the user defined designs without getting lost in the complexity. Also we have prepared a user guide how to design an operating system on hardware based computer architecture from scratch. The developed operating system is written using assembly language of our computer architecture named BZK.SAU and presented an educational tool to the literatur

Scratchpad Memory Management For Multicore Real-Time Embedded Systems

Multicore systems will continue to spread in the domain of real-time embedded systems due to the increasing need for high-performance applications. This research discusses some of the challenges associated with employing multicore systems for safety-critical real-time applications. Mainly, this work is concerned with providing: 1) efficient inter-core timing isolation for independent tasks, and 2) predictable task communication for communicating tasks. Principally, we introduce a new task execution model, based on the 3-phase execution model, that exploits the Direct Memory Access (DMA) controllers available in modern embedded platforms along with ScratchPad Memories (SPMs) to enforce strong timing isolation between tasks. The DMA and the SPMs are explicitly managed to pre-load tasks from main memory into the local (private) scratchpad memories. Tasks are then executed from the local SPMs without accessing main memory. This model allows CPU execution to be overlapped with DMA loading/unloading operations from and to main memory. We show that by co-scheduling task execution on CPUs and using DMA to access memory and I/O, we can efficiently hide access latency to physical resources. In turn, this leads to significant improvements in system schedulability, compared to both the case of unregulated contention for access to physical resources and to previous cache and SPM management techniques for real-time systems. The presented SPM-centric scheduling algorithms and analyses cover single-core, partitioned, and global real-time systems. The proposed scheme is also extended to support large tasks that do not fit entirely into the local SPM. Moreover, the schedulability analysis considers the case of recovering from transient soft errors (bit flips caused by a single event upset) in several levels of memories, that cannot be automatically corrected in hardware by the ECC unit. The proposed SPM-centric scheduling is integrated at the OS level; thus it is transparent to applications. The proposed scheme is implemented and evaluated on an FPGA platform and a Commercial-Off-The-Shelf (COTS) platform. In regards to real-time task communication, two types of communication are considered. 1) Asynchronous inter-task communication, between either sequential tasks (single-threaded) or parallel tasks (multi-threaded). 2) Intra-task communication, where parallel threads of the same application exchange data. A new task scheduling model for parallel tasks (Bundled Scheduling) is proposed to facilitate intra-task communication and reduce synchronization overheads. We show that the proposed bundled scheduling model can be applied to several parallel programming models, such as fork-join and DAG-based applications, leading to improved system schedulability. Finally, intra-task communication is governed by a predictable inter-core communication platform. Specifically, we propose HopliteRT, a lean and predictable Network-on-Chip that connects the private SPMs