Power system security assessment through analog computation

This dissertation proposes a methodology for power system security assessment through analog computation. By exploiting the strengths of analog computation a more robust security assessment can be performed as compared to traditional methods. Security assessment is currently performed by power system operators utilizing digital computers and determines the power system structure, states and level of security based on telemetered data and knowledge of the system. Ideally this process would occur in real time but due to the limitations of digital computers and telemetry systems the security assessment is currently conducted at periodic intervals of ten to fifteen minutes. This process requires a tremendous amount of computation for large systems. In order to provide updated assessment at such time intervals, not even in real time, numerous assumptions and simplifications of the power system models and analyses are required to simplify and speed up the digital computations. Due to its inherent speed and computational efficiency analog computation is proving to be a viable alternative.Analog computation by definition is continuous in time and embodies an entirely different paradigm to computing as compared to discrete time methods. Security assessment for digital computers consists of topology estimations, state estimation and contingency analysis. The theory and practical approaches to these tasks through digital, discrete time, computational methods are fairly mature at this point in time but do not translate directly to analog computation. A robust analog computation engine along with corresponding computational theory is required in order to make use of analog methods for power system security assessment. This dissertation provides the relevant theory, hardware realization and application of an analog computer for power system security assessment.Ph.D., Electrical Engineering -- Drexel University, 200

Polynomial differential equations compute all real computable functions on computable compact intervals

In the last decade, the eld of analog computation has experienced renewed interest. In particular, there have been several attempts to un- derstand which relations exist between the many models of analog com- putation. Unfortunately, most models are not equivalent. It is known that Euler's Gamma function is computable according to computable analysis, while it cannot be generated by Shannon's General Purpose Analog Computer (GPAC). This example has often been used to argue that the GPAC is less powerful than digital computation. However, as we will demonstrate, when computability with GPACs is not restricted to real-time generation of functions, we obtain two equiva- lent models of analog computation. Using this approach, it has been shown recently that the Gamma func- tion becomes computable by a GPAC [1]. Here we extend this result by showing that, in an appropriate framework, the GPAC and computable analysis are actually equivalent from the computability point of view, at least in compact intervals. Since GPACs are equivalent to systems of polynomial di erential equations then we show that all real computable functions over compact intervals can be de ned by such models

Hybrid Analog-Digital Co-Processing for Scientific Computation

In the past 10 years computer architecture research has moved to more heterogeneity and less adherence to conventional abstractions. Scientists and engineers hold an unshakable belief that computing holds keys to unlocking humanity's Grand Challenges. Acting on that belief they have looked deeper into computer architecture to find specialized support for their applications. Likewise, computer architects have looked deeper into circuits and devices in search of untapped performance and efficiency. The lines between computer architecture layers---applications, algorithms, architectures, microarchitectures, circuits and devices---have blurred. Against this backdrop, a menagerie of computer architectures are on the horizon, ones that forgo basic assumptions about computer hardware, and require new thinking of how such hardware supports problems and algorithms. This thesis is about revisiting hybrid analog-digital computing in support of diverse modern workloads. Hybrid computing had extensive applications in early computing history, and has been revisited for small-scale applications in embedded systems. But architectural support for using hybrid computing in modern workloads, at scale and with high accuracy solutions, has been lacking. I demonstrate solving a variety of scientific computing problems, including stochastic ODEs, partial differential equations, linear algebra, and nonlinear systems of equations, as case studies in hybrid computing. I solve these problems on a system of multiple prototype analog accelerator chips built by a team at Columbia University. On that team I made contributions toward programming the chips, building the digital interface, and validating the chips' functionality. The analog accelerator chip is intended for use in conjunction with a conventional digital host computer. The appeal and motivation for using an analog accelerator is efficiency and performance, but it comes with limitations in accuracy and problem sizes that we have to work around. The first problem is how to do problems in this unconventional computation model. Scientific computing phrases problems as differential equations and algebraic equations. Differential equations are a continuous view of the world, while algebraic equations are a discrete one. Prior work in analog computing mostly focused on differential equations; algebraic equations played a minor role in prior work in analog computing. The secret to using the analog accelerator to support modern workloads on conventional computers is that these two viewpoints are interchangeable. The algebraic equations that underlie most workloads can be solved as differential equations, and differential equations are naturally solvable in the analog accelerator chip. A hybrid analog-digital computer architecture can focus on solving linear and nonlinear algebra problems to support many workloads. The second problem is how to get accurate solutions using hybrid analog-digital computing. The reason that the analog computation model gives less accurate solutions is it gives up representing numbers as digital binary numbers, and instead uses the full range of analog voltage and current to represent real numbers. Prior work has established that encoding data in analog signals gives an energy efficiency advantage as long as the analog data precision is limited. While the analog accelerator alone may be useful for energy-constrained applications where inputs and outputs are imprecise, we are more interested in using analog in conjunction with digital for precise solutions. This thesis gives novel insight that the trick to do so is to solve nonlinear problems where low-precision guesses are useful for conventional digital algorithms. The third problem is how to solve large problems using hybrid analog-digital computing. The reason the analog computation model can't handle large problems is it gives up step-by-step discrete-time operation, instead allowing variables to evolve smoothly in continuous time. To make that happen the analog accelerator works by chaining hardware for mathematical operations end-to-end. During computation analog data flows through the hardware with no overheads in control logic and memory accesses. The downside is then the needed hardware size grows alongside problem sizes. While scientific computing researchers have for a long time split large problems into smaller subproblems to fit in digital computer constraints, this thesis is a first attempt to consider these divide-and-conquer algorithms as an essential tool in using the analog model of computation. As we enter the post-Moore’s law era of computing, unconventional architectures will offer specialized models of computation that uniquely support specific problem types. Two prominent examples are deep neural networks and quantum computers. Recent trends in computer science research show these unconventional architectures will soon have broad adoption. In this thesis I show another specialized, unconventional architecture is to use analog accelerators to solve problems in scientific computing. Computer architecture researchers will discover other important models of computation in the future. This thesis is an example of the discovery process, implementation, and evaluation of how an unconventional architecture supports specialized workloads

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Implementation of recursive algorithms for delay-time estimation using the fast Walsh transform

Use of the fast Walsh transform to resolve noisy signals into Walsh function series to digitally implement maximum-likelihood parameter estimators for real-time use is investigated. Realization of estimators which seek a null in the derivative of the log-likelihood function, instead of direct maximization, results in feedback algorithms which yield considerable savings in computation time and storage. Performance of these feedback delay-estimation algorithms is characterized in terms of mean-squared error (MSE) and response to a delay step by Monte Carlo simulation. The effect of changing the number of points in the transform on the MSE is also investigated. Hard limiting of the estimator input signal is simulated to represent the limited range of an analog-to-digital converter. Initial time estimates indicate that it is indeed feasible to use the algorithms presented to perform delay estimation in real time. The relative merits of implementing estimators with dedicated hardware, software, and/or firmware is also discussed --Abstract, page ii

The Resilience of Computationalism

Computationalism—the view that cognition is computation—has always been controversial. It faces two types of objection. According to insufficiency objections, computation is insufficient for some cognitive phenomenon X. According to objections from neural realization, cognitive processes are realized by neural processes, but neural processes have feature Y and having Y is incompatible with being (or realizing) computations. In this paper, I explain why computationalism has survived these objections. Insufficiency objections are at best partial: for all they establish, computation may be sufficient for cognitive phenomena other than X, may be part of the explanation for X, or both. Objections from neural realization are based either on a false contrast between feature Y and computation or on an account of computation that is too vague to yield the desired conclusion. To adjudicate the dispute between computationalism and its foes, I will conclude that we need a better account of computation

The importance of space and time in neuromorphic cognitive agents

Artificial neural networks and computational neuroscience models have made tremendous progress, allowing computers to achieve impressive results in artificial intelligence (AI) applications, such as image recognition, natural language processing, or autonomous driving. Despite this remarkable progress, biological neural systems consume orders of magnitude less energy than today's artificial neural networks and are much more agile and adaptive. This efficiency and adaptivity gap is partially explained by the computing substrate of biological neural processing systems that is fundamentally different from the way today's computers are built. Biological systems use in-memory computing elements operating in a massively parallel way rather than time-multiplexed computing units that are reused in a sequential fashion. Moreover, activity of biological neurons follows continuous-time dynamics in real, physical time, instead of operating on discrete temporal cycles abstracted away from real-time. Here, we present neuromorphic processing devices that emulate the biological style of processing by using parallel instances of mixed-signal analog/digital circuits that operate in real time. We argue that this approach brings significant advantages in efficiency of computation. We show examples of embodied neuromorphic agents that use such devices to interact with the environment and exhibit autonomous learning