Hardware-Software Cosynthesis for Digital Systems

As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique problems. The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. System functionality is captured using the HardwareC hardware description language. The synthesis of an Ethernet-based network coprocessor is discussed as an example

Plataforma de desarrollo tecnológico de sistemas digitales basada en FPGA

This work is a research, technological development and innovation project where design, development, building and implementation of a FPGA-based digital systems technological development platform are shown. This work was developed along with the INSTECH S.A.P.I. de C.V. company, the platform was submitted for industrial protection at IMPI under the little patent category. This work is focused in the platform design strategy for making it outstand among the many options currently available in the market and it targets a regional market seeking adaptability rather than specialization. CONACYT’s National Laboratory in Embedded Systems, Advanced Electronic Design, and Microsystems (SEDEAM), which is part of the Industrial Technological Research and Innovation Center (CIITI) at Electric Engineering Academic Unit (UAIE) from Universidad Autónoma de Zacatecas, enabled this thesis’ development with the acquisition, installation and start-up of its PCBs prototype assembly line. Besides the design and implementation of the platform, an application focused in digital radiography tested initially in the platform and then ported towards an application specific design. The radiography solution was submitted for industrial protection to the Mexican Institute for Intellectual Protection under the patent category.El presente trabajo es un proyecto de investigación, desarrollo tecnológico e innovación donde se muestra el diseño, desarrollo, construcción e implementación de una plataforma de desarrollo tecnológico de sistemas digitales basada en FPGA. Este trabajo se desarrolló en conjunto con la empresa INSTECH S.A.P.I. de C.V. y la plataforma fue sometida ante el Instituto Mexicano de la Propiedad Industrial (IMPI) para su protección industrial bajo la figura de modelo de utilidad. En la presente tesis se explica a detalle la estrategia de diseño de dicha plataforma y sus diferencias con las otras opciones que existen actualmente en el mercado, destacando su enfoque hacia un mercado regional que busca adaptabilidad por sobre especialización. El Laboratorio Nacional CONACYT en Sistemas Embebidos, Diseño Electrónico Avanzado y Microsistemas (SEDEAM), que forma parte del Centro de Investigación e Innovación Tecnológica Industrial (CIITI) en la Unidad Académica de Ingeniería Eléctrica (UAIE) de la Universidad Autónoma de Zacatecas, facilitó el desarrollo de esta tesis con la adquisición, instalación y puesta en marcha de su línea de desarrollo de prototipos de PCBs. Además del diseño e implementación de la plataforma, se presenta una aplicación enfocada en radiografía digital probada inicialmente en la plataforma y portada posteriormente hacia un diseño de aplicación específico. La solución de radiografía fue sometida ante el IMPI para su protección industrial bajo la figura de patente

Hierarchical Transactions for Hardware/Software Cosynthesis

Modern heterogeneous devices provide of a variety of computationally diverse components holding tremendous performance and power capability. Hardware-software cosynthesis offers system-level synthesis and optimization opportunities to realize the potential of these evolving architectures. Efficiently coordinating high-throughput data to make use of available computational resources requires a myriad of distributed local memories, caching structures, and data motion resources. In fact, storage, caching, and data transfer components comprise the majority of silicon real estate. Conventional automated approaches, unfortunately, do not effectively represent applications in a way that captures data motion and state management which dictate dominant system costs. Consequently, existing cosynthesis methods suffer from poor utility of computational resources. Automated cosynthesis tailored towards memory-centric optimizations can address the challenge, adapting partitioning, scheduling, mapping, and binding techniques to maximize overall system utility.This research presents a novel hierarchical transaction model that formalizes state and control management through an abstract data/control encapsulation semantic. It is designed from the ground-up to enable efficient synthesis across heterogeneous system components, with an emphasis on memory capacity constraints. It intrinsically encourages a high degree of concurrency and latency tolerance, and provides verification tools to ensure correctness. A unique data/execution hierarchical encapsulation framework guarantees scalable analysis, supporting a novel concept of state and control mobility. A front-end language allows concise expression of designer intent, and is structured with synthesis in mind. Designers express families of valid executions in a minimal format through high-level dependencies, type systems, and computational relationships, allowing synthesis tools to manage lower-level details. This dissertation introduces and exercises the model, discussing language construction, demonstrating control and data-dominated applications, and presenting a synthesis path that exhibits near-linear scalability with problem size

An object-based codesign methodology.

The research into Codesign of Hardware and Software stems from the development of embedded systems, on which various systems restrictions are imposed. Typical restrictions can be the overall time (latency) to complete an assigned function and the space/power limits within the system. Although software can be used to undertake most tasks in an embedded system, ASIC (Application Specific Integrated Circuits) hardware components sometimes have to be recruited to meet the system constraints. Designing the restricted embedded system with both software and hardware components in it involves the analysis of not only individual hardware/software components but also their mutual influences. Using co-design principles, the approach is to consider both hardware and software from a coherent viewpoint.This thesis presents the results from our research project in the area of Codesign of Hardware and Software. In this project, we investigated previously published codesign approaches and their methodological supports. The investigation has identified shortcomings and problems with the existing codesign methodologies. A new object-based codesign approach (Co-PARSE) is thus developed in this project, which is supported by successive phases, guidelines, and techniques. This methodology offers a coherent design framework for real-time embedded systems and incorporates the criteria of system performance and hardware cost. Tools have been developed to facilitate the use of the methodology. Within the methodology, a high-level system modeling and specification approach has been developed and formalised in the Co-BSL (Codesign Behavior Specification Language). The means of transforming Co-BSL specifications to C and VHDL implementations is defined, and a library of VHDL components provided. The thesis documents the partitioning approach taken within the methodology and proposes a new multi-layered bus architecture as a basis for more flexible and efficient implementations. A means of simulating the performance characteristics of this architecture under different configurations is provided, and examples of simulation results are presented. A new embedded system (the Radio Data Computing System) is designed and simulated in the Co-PARSE methodology and simulation results analysed. The thesis concludes with an evaluation of the work carried out in the project and proposals for extending the results obtained in future research.The major contributions reported in this thesis can be summarised as follows. First, the unified system specification means has been designed, which is embodied in the Co-BSL. It captures overall dynamic aspects and performance constraints in the system under development. This high-level specification language is independent of implementation and does not bias the designer towards the use of hardware or software components at this early stage. Second, within Co-PARSE, the target architecture of the system under development has been exploited to improve the system performance and at the same time to reduce hardware cost. This novel concept has been realised by the introduction of an asynchronous bus protocol and the multi-layer bus communication structure. Third, in order to evaluate the strength and practicability of the Co-PARSE methodology, an extensive case study has been carried out. The new RDC (Radio Dada Computing) System has been designed in the proposed codesign approach. Codesign phases are subsequently applied and the guidelines and tools that are specially developed in support of the methodology are fully utilized