Installed performance assessment of a boundary layer ingesting distributed propulsion system at design point

Boundary layer ingesting systems have been proposed as a concept with great potential for reducing the fuel consumption of conventional propulsion systems and the overall drag of an aircraft. These studies have indicated that if the aerodynamic and efficiency losses were minimised, the propulsion system demonstrated substantial power consumption benefits in comparison to equivalent propulsion systems operating in free stream flow. Previously assessed analytical methods for BLI simulation have been from an uninstalled perspective. This research will present the formulation of an rapid analytical method for preliminary design studies which evaluates the installed performance of a boundary layer ingesting system. The method uses boundary layer theory and one dimensional gas dynamics to assess the performance of an integrated system. The method was applied to a case study of the distributed propulsor array of a blended wing body aircraft. There was particular focus on assessment how local flow characteristics influence the performance of individual propulsors and the propulsion system as a whole. The application of the model show that the spanwise flow variation has a significant impact on the performance of the array as a whole. A clear optimum design point is identified which minimises the power consumption for an array with a fixed configuration and net propulsive force requirement. In addition, the sensitivity of the system to distortion related losses is determined and a point is identi ed where a conventional free-stream propulsor is the lower power option. Power saving coefficient for the configurations considered is estimated to lie in the region of 15%

An improved instruction-level power model for ARM11 microprocessor

The power and energy consumed by a chip has become the primary design constraint for embedded systems, which has led to a lot of work in hardware design techniques such as clock gating and power gating. The software can also affect the power usage of a chip, hence good software design can be used to reduce the power further. In this paper we present an instruction-level power model based on an ARM1176JZF-S processor to predict the power of software applications. Our model takes substantially less input data than existing high accuracy models and does not need to consider each instruction individually. We show that the power is related to both the distribution of instruction types and the operations per clock cycle (OPC) of the program. Our model does not need to consider the effect of two adjacent instructions, which saves a lot of calculation and measurements. Pipeline stall effects are also considered by OPC instead of cache miss, because there are a lot of other reasons that can cause the pipeline to stall. The model shows good performance with a maximum estimation error of -8.28\% and an average absolute estimation error is 4.88\% over six benchmarks. Finally, we prove that energy per operation (EPO) decreases with increasing operations per clock cycle, and we confirm the relationship empirically

Formal and Informal Methods for Multi-Core Design Space Exploration

We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.Comment: In Proceedings QAPL 2014, arXiv:1406.156

A software controlled voltage tuning system using multi-purpose ring oscillators

This paper presents a novel software driven voltage tuning method that utilises multi-purpose Ring Oscillators (ROs) to provide process variation and environment sensitive energy reductions. The proposed technique enables voltage tuning based on the observed frequency of the ROs, taken as a representation of the device speed and used to estimate a safe minimum operating voltage at a given core frequency. A conservative linear relationship between RO frequency and silicon speed is used to approximate the critical path of the processor. Using a multi-purpose RO not specifically implemented for critical path characterisation is a unique approach to voltage tuning. The parameters governing the relationship between RO and silicon speed are obtained through the testing of a sample of processors from different wafer regions. These parameters can then be used on all devices of that model. The tuning method and software control framework is demonstrated on a sample of XMOS XS1-U8A-64 embedded microprocessors, yielding a dynamic power saving of up to 25% with no performance reduction and no negative impact on the real-time constraints of the embedded software running on the processor

Therblig-embedded value stream mapping method for lean energy machining

To improve energy efficiency, extensive studies have focused on the cutting parameters optimization in the machining process. Actually, non-cutting activities (NCA) occur frequently during machining and this is a promising way to save energy through optimizing NCA without changing the cutting parameters. However, it is difficult for the existing methods to accurately determine and reduce the energy wastes (EW) in NCA. To fill this gap, a novel Therblig-embedded Value Stream Mapping (TVSM) method is proposed to improve the energy transparency and clearly show and reduce the EW in NCA. The Future-State-Map (FSM) of TVSM can be built by minimizing non-cutting activities and Therbligs. By implementing the FSM, time and energy efficiencies can be improved without decreasing the machining quality, which is consistent with the goal of lean energy machining. The method is validated by a machining case study, the results show that the total energy is reduced by 7.65%, and the time efficiency of the value-added activities is improved by 8.12% , and the energy efficiency of value-added activities and Therbligs are raised by 4.95% and 1.58%, respectively. This approach can be applied to reduce the EW of NCA, to support designers to design high energy efficiency machining processes during process planning

Design Space Exploration in Cyber-Physical Systems

Cyber physical systems (CPS) integrate a variety of engineering areas such as control, mechanical and computer engineering in a holistic design effort. While interdependencies between the different disciplines are key attributes of CPS design science, little is known about the impact of design decisions of the cyber part on the overall system qualities. To investigate these interdependencies, this paper proposes a simulation-based Design Space Exploration (DSE) framework that considers detailed cyber system parameters such as cache size, bus width, and voltage levels in addition to physical and control parameters of the CPS. We propose an exploration algorithm that surfs the parameter configurations in the cyber physical sub-systems, in order to approximate the Pareto-optimal design points with regards to the trade-os among the design objectives, such as energy consumption and control stability. We apply the proposed framework to a network control system for an inverted-pendulum application. The presented holistic evaluation of the identified Pareto-points reveals the presence of non-trivial trade-os, which are imposed by the control, physical, and detailed cyber parameters. For instance the identified energy and control optimal design points comprise configurations with a wide range of CPU speeds, sample times and cache configuration following non-trivial zig-zag patterns. The proposed framework could identify and manage those trade-os and, as a result, is an imperative rst step to automate the search for superior CSP configurations

Real-Time Dense Stereo Matching With ELAS on FPGA Accelerated Embedded Devices

For many applications in low-power real-time robotics, stereo cameras are the sensors of choice for depth perception as they are typically cheaper and more versatile than their active counterparts. Their biggest drawback, however, is that they do not directly sense depth maps; instead, these must be estimated through data-intensive processes. Therefore, appropriate algorithm selection plays an important role in achieving the desired performance characteristics. Motivated by applications in space and mobile robotics, we implement and evaluate a FPGA-accelerated adaptation of the ELAS algorithm. Despite offering one of the best trade-offs between efficiency and accuracy, ELAS has only been shown to run at 1.5-3 fps on a high-end CPU. Our system preserves all intriguing properties of the original algorithm, such as the slanted plane priors, but can achieve a frame rate of 47fps whilst consuming under 4W of power. Unlike previous FPGA based designs, we take advantage of both components on the CPU/FPGA System-on-Chip to showcase the strategy necessary to accelerate more complex and computationally diverse algorithms for such low power, real-time systems.Comment: 8 pages, 7 figures, 2 table