Using an FPGA for Fast Bit Accurate SoC Simulation

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy

A statistical bit error generator for emulation of complex forward error correction schemes

Forward error correction (FEC schemes are generally used in wireless communication systems to maintain an acceptable quality of service. Various models have been proposed in literature to predict the end-to-end quality of wireless video systems. However, most of these models utilize simplistic error generators which do not accurately represent any practical wireless channel. A more accurate way is to evaluate the quality of a video system using Monte Carlo techniques. However these necessitate huge computational times, making these methods unpractical. This paper proposes an alternative method that can be used in modeling of complex communications systems with minimal computational time. The proposed three random variable method was used to model two FEC schemes adopted by the digital video broadcasting (DVB) standard. Simulation results confirm that this method closely matches the performance of the considered communication systems in both bit error rate (BER) and peak signal-to-noise ratio (PSNR).peer-reviewe

Configurable LDPC Decoder Architecture for Regular and Irregular Codes

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.NokiaNational Science Foundatio

A low-complexity linear and iterative receiver architecture for multi-antenna communication systems

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Vita.Includes bibliographical references (leaves 60-62).Multi-antenna systems have been shown to significantly improve channel capacity in wireless environments. The focus of this thesis is on the design of low-complexity multi-antenna receiver architectures for communication networks and their demonstration in a real-time wireless environment. Our practical realization of an orthogonal frequency-division multi-antenna receiver is capable of several forms of linear and iterative detection. Our implementation is based on a division-free reformulation of standard minimum mean-squared-error detection algorithms and uses complex dot-products as the basic building blocks of a folded-pipelined architecture. This folded-pipelined architecture provides significant area savings over non-folded approaches. The demonstration of our receiver architecture is carried out on a rapid-prototyping FPGA communication system. This prototype is used to validate our design and complement theoretical and simulated results with real-time laboratory measurements in a typical office environment.by David Louis Milliner.M.Eng

Improve the Usability of Polar Codes: Code Construction, Performance Enhancement and Configurable Hardware

Error-correcting codes (ECC) have been widely used for forward error correction (FEC) in modern communication systems to dramatically reduce the signal-to-noise ratio (SNR) needed to achieve a given bit error rate (BER). Newly invented polar codes have attracted much interest because of their capacity-achieving potential, efficient encoder and decoder implementation, and flexible architecture design space.This dissertation is aimed at improving the usability of polar codes by providing a practical code design method, new approaches to improve the performance of polar code, and a configurable hardware design that adapts to various specifications. State-of-the-art polar codes are used to achieve extremely low error rates. In this work, high-performance FPGA is used in prototyping polar decoders to catch rare-case errors for error-correcting performance verification and error analysis. To discover the polarization characteristics and error patterns of polar codes, an FPGA emulation platform for belief-propagation (BP) decoding is built by a semi-automated construction flow. The FPGA-based emulation achieves significant speedup in large-scale experiments involving trillions of data frames. The platform is a key enabler of this work. The frozen set selection of polar codes, known as bit selection, is critical to the error-correcting performance of polar codes. A simulation-based in-order bit selection method is developed to evaluate the error rate of each bit using Monte Carlo simulations. The frozen set is selected based on the bit reliability ranking. The resulting code construction exhibits up to 1 dB coding gain with respect to the conventional bit selection. To further improve the coding gain of BP decoder for low-error-rate applications, the decoding error mechanisms are studied and analyzed, and the errors are classified based on their distinct signatures. Error detection is enabled by low-cost CRC concatenation, and post-processing algorithms targeting at each type of the error is designed to mitigate the vast majority of the decoding errors. The post-processor incurs only a small implementation overhead, but it provides more than an order of magnitude improvement of the error-correcting performance. The regularity of the BP decoder structure offers many hardware architecture choices. Silicon area, power consumption, throughput and latency can be traded to reach the optimal design points for practical use cases. A comprehensive design space exploration reveals several practical architectures at different design points. The scalability of each architecture is also evaluated based on the implementation candidates. For dynamic communication channels, such as wireless channels in the upcoming 5G applications, multiple codes of different lengths and code rates are needed to t varying channel conditions. To minimize implementation cost, a universal decoder architecture is proposed to support multiple codes through hardware reuse. A 40nm length- and rate-configurable polar decoder ASIC is demonstrated to fit various communication environments and service requirements.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/140817/1/shuangsh_1.pd

Design for manufactureability with regular fabrics in digital integrated circuits

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 113-115).Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. This research addresses both ideas, by examining integrated circuit design styles and aspects that can help curb process variation and improve manufacturability and performance in future technology generations. One suggested method to reduce variation sensitivity in system designs has been the concept of design regularity. Long used in FPGAs, and SRAMs, the concept of repeatable blocks is examined in this work as a method of reducing circuit variation. Layout based variation is examined in three designs with different distinctions of regularity: a Via-Patterned Gate Array (VPGA) FPU, a Berkeley BEE-generated decoder, and a low power FPGA. The circuit level impact on variation is also considered, by examining several circuit architectures. This includes analysis of the novel Limited Switch Dynamic Logic (LSDL) style, which reduces design area and encourages regularity through minimum logic sizing.(cont.) Robustness to spatial variation and slanted plane effects is examined with a common-centroid based layout methodology for digital integrated circuits. Finally, a methodology is introduced in the form of the Monte Carlo Variation Analysis Engine whereby distributed process variables are fed into repeated simulation runs, output metrics are recorded, and regressions are measured to expose design sensitivities. The results for different layout and circuit design styles identify improvements that may be made to improve robustness to variation. We show that design regularity is a significant factor in mitigating sensitivity to process variation and is worthy of further examination.by Mehdi Gazor.S.M

Rapid design and analysis of communication systems using the BEE hardware emulation environment

This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and design environment for communication and digital signal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (Application Specific Integrated Circuits) equivalent gates at an overall system clock rate up to 60 MHz. This translates to over 600 billion 16-bit additions (operations) per second on one unit. An integrated software design flow enables the users to specify the design using a data-flow diagram, then automatically generates both the FPGA implementation for real-time rapid prototyping and a cycle-accurate, bit-true, and functionally equivalent ASIC implementation. For system-level design, the BEE hardware and software support rapid design turn-around and early performance analysis, without full synthesis or hardware mapping, from the high-level design entry. A case study detailing a turbo-decoder explains how the processing capability of the emulator can be utilized to verify a design using one billion input vectors with a speed-up factor exceeding 10 6 over equivalent software simulation methods.