Rail-to-Rail Operational in Low-Power Reconfigurable Analog Circuitry

Analog signal processing (ASP) can be used to decrease energy consumption by several orders of magnitude over completely digital applications. Low-power field programmable analog arrays (FPAA) have been previously used by analog designers to decrease energy consumption. Combining ASP with an FPAA, energy consumption of these systems can be further reduced. For ASP to be most functional, it must achieve rail-to-rail operation to maintain a high dynamic range. This work strives to further reduce power consumption in reconfigurable analog circuitry by presenting a novel data converter that utilizes ASP and rail-to-rail operation. Rail-to-Rail operation is achieved in the data converter with the use of an operational amplifier presented in this work. This efficient yet elementary data converter has been fabricated in a 0.5$\mu$m standard CMOS process. Additionally, this work looks deeper into the challenges of students working remotely, how MATLAB can be used to create circuit design tools, and how these developmental tools can be used by circuit design students

Achieving rail-to-rail input operation using level-shift multiplexing technique for all CMOS op-amps

This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation

CMOS operational amplifiers with continuous-time capacitive common mode feedback

A simple and power efficient approach for the implementation of continuous-time common mode feedback networks using a capacitive averaging network is introduced. It is shown that low voltage, continuous-time, fully differential rail to rail operation can be achieved using the proposed technique. This at the expense of very small additional hardware and no additional power dissipation One stage, two stage, telescopic and folded cascode op-amps are discussed as application examples

Class-AB rail-to-rail CMOS buffer with bulk-driven super source followers

This paper describes a rail-to-rail CMOS analog voltage buffer designed to have extremely low static current consumption as well as high current drive capability. The buffer employs a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilized to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. The simulated results are provided to demonstrate that the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, whilst the static current consumption remains under 8 muA

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs for Flexible X-Ray Detector

ECR/2017/000931 POCI-01-0145-FEDER-007688This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, $V_{DD}$ and $V_{SS}$ , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.publishersversionpublishe

High voltage command board (CREAM experiment)

Board which realize the interface between the CREAM experiment primary computer unit and the High Voltage generator units (2 x 50 units) located near the PMT matrix

A low-voltage Op Amp with rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage

In this paper a low-voltage two-stage Op Amp is presented. The Op Amp features rail-to-rail operation and has an @put stage with a constant transconductance (%) over the entire common-mode input range. The input stage consists of an n- and a PMOS differential pair connected in parallel. The constant gm is accomplished by regulating the tail-currents with the aid of an MOS translinear (MTL) circuit. The resulting gn is constant within 5% The common-source output stage employs a feedback circuit which also contains an MTL circuit. This feedback circuit ensures class AB operation and prevents the transistors in the output stage from cutting off. The Op Amp will be realized in a semi custom CMOS process with minimum channel lengths of 1Opm. Simulations show that the minimum supply voltage is less than 2.5 V. A unity gain bandwidth of 550 kHz and a DC voltage gain larger than 80 dB are feasible. The input range exceeds the supply rails, whereas the output range reaches the rails within 130 mV

Time interleaved optical sampling for ultra-high speed A/D conversion

A scheme is proposed for increasing the sampling rate of analogue-to-digital conversion by more than an order of magnitude by combining state-of-the-art A/D converters with photonic technology. Ultra-high speed sampling is performed optically by a multiwavelength pulse train. Wavelength demultiplexers convert the high repetition rate data stream of samples into parallel data streams that can be handled by available electronic A/D converters

A tunable floating-gate CMOS transconductor based on current multiplication

In this paper a novel transconductor based on floating gate techniques that performs current multiplication for tuning is presented. The multiplication is achieved using transistors operating in weak and moderate inversion together with floating voltage sources implemented conveniently by floating capacitors. Besides, a tuning scheme is proposed to set the transconductance parameter accurately. The resulting circuit features compactness, low voltage operation, and rail-to-rail input range. Measurement and simulation results using a 0.5um CMOS technology are presented to confirm all the circuits and strategies proposed