Four-quadrant one-transistor-synapse for high-density CNN implementations

Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.Comisión Interministerial de Ciencia y Tecnología TIC96- 1392-C02-0

Phased Array Systems in Silicon

Phased array systems, a special case of MIMO systems, take advantage of spatial directivity and array gain to increase spectral efficiency. Implementing a phased array system at high frequency in a commercial silicon process technology presents several challenges. This article focuses on the architectural and circuit-level trade-offs involved in the design of the first silicon-based fully integrated phased array system operating at 24 GHz. The details of some of the important circuit building blocks are also discussed. The measured results demonstrate the feasibility of using integrated phased arrays for wireless communication and vehicular radar applications at 24 GHz

RF oscillators

2021/20222n quadrimestr

Simulating and Designing RF Transmitter for Small Satellites

This paper discusses the simulation and the design of an RF transmitter for small satellites operating in the commercial S- band (2.2 - 2.29 GHz) with a data rate of 8Mbps. In such systems, modelling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. In order to provide efficient and accurate simulation for the transmitter circuits, simple macromodels for weakly nonlinear mixer and power amplifier are used in the system simulation. Also, we introduce the noise in several circuits (frequency synthesizer, crystal oscillator, power amplifier, mixer,…) and we demonstrate their effect on the noise performance system. In the simulation we consider features of components and technologies commercially available

Using Variable Width RF Integrated Inductors for Quality Factor Optimization

Part 20: Electronics: RF ApplicationsInternational audienceThe advancement of CMOS technology led to the integration of more complex functions. In the particular of wireless transceivers, integrated LC tanks are becoming popular both for VCOs and integrated filters [1]. For RF applications the main challenge is still the design of integrated inductors with the maximum quality factor. For that purpose, tapered, i.e., variable width inductors have been proposed in the literature. In this paper, analytical expressions for the determination the pi-model parameters, for the characterization of variable width integrated inductors are proposed. The expressions rely exclusively on geometrical and technological parameters, thus granting the rapid adaptation of the model to different technologies. The results obtained with the model are compared against simulation with ASITIC, showing errors below 10%. The model is then integrated into an optimization procedure where inductors with a quality factor improvement in the order of 20-30% are obtained, when compared with fixed width inductors

A Low Power 5.8GHz Fully Integrated CMOS LNA for Wireless Applications

A low power 5.8 GHz fully integrated CMOS low noise amplifier (LNA) with on chip spiral inductors for wireless applications is designed based on TSMC 0.18 µm technology in this paper. The cascode structure and power-constrained simultaneous noise and input matching technique are adopted to achieve low noise, low power and high gain characteristics. The proposed LNA exhibit a state of the art performance consuming only 6.4mW from a 1.8V power supply. The simulation results show that it has a noise figure (NF) only 0.972 dB, which is perfectly close to NFmin while maintaining the other performances. The proposed LNA also has an input 1-dB compression point (IP1dB) of-21.22 dBm, a power gain of 17.04 dB, and good input and output reflection coefficients, which indicate that the proposed LNA topology is very suitable for the implementation of narrowband LNAs in 802.11a wireless applications

EM simulation assisted parameter extraction for transferred-substrate InP HBT modeling

AbstractIn this paper, an electromagnetic (EM) simulation assisted parameter extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated three-dimensional EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network provides accurate small-signal prediction up to 220 GHz.</jats:p

Joint symbol and chip synchronization for a burst-mode-communication superregenerative MSK receiver

In this paper we describe a superregenerative (SR) MSK receiver able to operate in a burst-mode framework where synchronization is required for each packet. The receiver is based on an SR oscillator which provides samples of the incoming instantaneous phase trajectories. We develop a simple yet effective technique to achieve joint chip and symbol synchronization within the time limits of a suitable preamble. We develop some general results and focus on the case of the IEEE 802.15.4 MSK physical layer. We provide details on a VHDL implementation on an FPGA where the most complex digital processing block is an accumulator. Simulation and experimental results are provided to validate the described technique.Peer ReviewedPostprint (published version