Timed array antenna system : application to wideband and ultra-wideband beamforming receivers

Antenna array systems have a broad range of applications in radio frequency (RF) and ultra-wideband (UWB) communications to receive/transmit electromagnetic waves from/to the sky. They can enhance the amplitude of the input signals, steer beams electronically, and reject interferences thanks to beamforming technique. In an antenna array beamforming system, delay cells with the tunable capability of delay amount compensate the relative delay of signals received by antennas. In fact, each antenna almost acts individually depending upon time delaying effects on the input signals. As a result, the delay cells are the basic elements of the beamforming systems. For this purpose, novel active true time delay (TTD) cells suitable for RF antenna arrays have been presented in this thesis. These active delay cells are based on 1st- and 2nd-order all-pass filters (APFs) and achieve quite a flat gain and delay within up to 10-GHz frequency range. Various techniques such as phase linearity and delay tunability have been accomplished to improve the design and performance. The 1st-order APF has been designed for a frequency range of 5 GHz, showing desirable frequency responses and linearity which is comparable with the state-of-the-art. This 1st-order APF is able to convert into a 2nd-order APF via adding a grounded capacitor. A compact 2nd-order APF using an active inductor has been also designed and simulated for frequencies up to 10 GHz. The active inductor has been utilized to tune the amount of delay and to reduce the on-chip size of the filter. In order to validate the performance of the delay cells, two UWB four-channel timed array beamforming receivers realized by the active TTD cells have been proposed. Each antenna channel exploits digitally controllable gain and delay on the input signal and demonstrates desirable gain and delay resolutions. The beamforming receivers have been designed for different UWB applications depending on their operating frequency ranges (that is, 3-5 and 3.1-10.6 GHz), and thus they have different system requirements and specifications. All the circuits and topologies presented in this dissertation have been designed in standard 180-nm CMOS technologies, featuring a unity gain frequency ( ft) up to 60 GHz.Els sistemes matricials d’antenes tenen una àmplia gamma d’aplicacions en radiofreqüència (RF) i comunicacions de banda ultraampla (UWB) per rebre i transmetre ones electromagnètics. Poden millorar l’amplitud dels senyals d’entrada rebuts, dirigir els feixos electrònicament i rebutjar les interferències gràcies a la tècnica de formació de feixos (beamforming). En un sistema beamforming de matriu d’antenes, les cèl·lules de retard amb capacitat ajustable del retard, compensen aquest retard relatiu dels senyals rebuts per les diferents antenes. De fet, cada antena gairebé actua individualment depenent dels efectes de retard de temps sobre el senyals d’entrada. Com a resultat, les cel·les de retard són els elements bàsics en el disseny dels actuals sistemes beamforming. Amb aquest propòsit, en aquesta tesi es presenten noves cèl·lules actives de retard en temps real (TTD, true time delay) adequades per a matrius d’antenes de RF. Aquestes cèl·lules de retard actives es basen en cèl·lules de primer i segon ordre passa-tot (APF), i aconsegueixen un guany i un retard força plans, en el rang de freqüència de fins a 10 GHz. Diverses tècniques com ara la linealitat de fase i la sintonització del retard s’han aconseguit per millorar el disseny i el rendiment. La cèl·lula APF de primer ordre s’ha dissenyat per a un rang de freqüències de fins a 5 GHz, mostrant unes respostes freqüencials i linealitat que són comparables amb l’estat de l’art actual. Aquestes cèl·lules APF de primer ordre es poden convertir en un APF de segon ordre afegint un condensador més connectat a massa. També s’ha dissenyat un APF compacte de segon ordre que utilitza una emulació d’inductor actiu per a freqüències de treball de fins a 10 GHz. S’ha utilitzat l'inductor actiu per ajustar la quantitat de retard introduït i reduir les dimensions del filtre al xip. Per validar les prestacions de les cel·les de retard propostes, s’han proposat dos receptors beamforming basats en matrius d’antenes de 4 canals, realitzats por cèl·lules TTD actives. Cada canal d’antena aprofita el guany i el retard controlables digitalment aplicats al senyal d’entrada, i demostra resolucions de guany i retard desitjables. Els receptors beamforming s’han dissenyat per a diferents aplicacions UWB segons els seus rangs de freqüències de funcionament (en aquest cas, 3-5 i 3,1-10,6 GHz) i, per tant, tenen diferents requisits i especificacions de disseny del sistema. Tots els circuits i topologies presentats en aquesta tesi s’han dissenyat en tecnologies CMOS estàndards de 180 nm, amb una freqüència de guany unitari (ft) de fins a 60 GHz.Postprint (published version

Tunable wide-band second-order all-pass filter-based time delay cell using active inductor

This paper presents a CMOS RF second-order voltage-mode all-pass filter (APF) as a time delay cell. The proposed filter benefits from a simple structure; consisting of one transistor, three resistors, and one grounded capacitor and inductor. The filter reaches a group delay of 60 ps over a 10 GHz bandwidth, while achieving maximum delay-bandwidth-product (DBW) and it consumes only 10.3 mW power. On the other hand, an active inductor is used in the APF instead of a passive RLC tank in order to control the time delay and improve the size. In this case, the power consumption increases while time delay can be tuned. The proposed APF is designed and simulated in a TSMC 180 nm CMOS process.Postprint (published version

Tunable wide–band second–order all–pass filter–based time delay cell using active inductor

Postprint (published version

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology

5GHz CMOS all-pass filter-based true time delay cell

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process.Postprint (published version

Tunable active inductor-based second-order all-pass filter as a time delay cell for multi-GHz operation

In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point P1dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P1dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.Peer ReviewedPostprint (author's final draft

CMOS RF first-order all-pass filter

In this paper, a wide-band first-order voltage-mode all-pass filter is presented. Due to a simple structure and appropriate performance of the proposed all-pass filter, this filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 4.5 GHz. The proposed circuit demonstrates a high linearity and consumes merely 16 mW power from a 1.8-V supply. Simulation results indicate an input-referred 1-dB compression point P1dB of 4.1 dBm and the wide-band operation capability of the first order all-pass filter. Furthermore, the proposed all-pass filter is capable of converting into a second-order all-pass filter adding only a grounded capacitor. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a TSMC 180-nm CMOS process.Postprint (published version

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Towards low-cost gigabit wireless systems at 60 GHz

The world-wide availability of the huge amount of license-free spectral space in the 60 GHz band provides wide room for gigabit-per-second (Gb/s) wireless applications. A commercial (read: low-cost) 60-GHz transceiver will, however, provide limited system performance due to the stringent link budget and the substantial RF imperfections. The work presented in this thesis is intended to support the design of low-cost 60-GHz transceivers for Gb/s transmission over short distances (a few meters). Typical applications are the transfer of high-definition streaming video and high-speed download. The presented work comprises research into the characteristics of typical 60-GHz channels, the evaluation of the transmission quality as well as the development of suitable baseband algorithms. This can be summarized as follows. In the first part, the characteristics of the wave propagation at 60 GHz are charted out by means of channel measurements and ray-tracing simulations for both narrow-beam and omni-directional configurations. Both line-of-sight (LOS) and non-line-of-sight (NLOS) are considered. This study reveals that antennas that produce a narrow beam can be used to boost the received power by tens of dBs when compared with omnidirectional configurations. Meanwhile, the time-domain dispersion of the channel is reduced to the order of nanoseconds, which facilitates Gb/s data transmission over 60-GHz channels considerably. Besides the execution of measurements and simulations, the influence of antenna radiation patterns is analyzed theoretically. It is indicated to what extent the signal-to-noise ratio, Rician-K factor and channel dispersion are improved by application of narrow-beam antennas and to what extent these parameters will be influenced by beam pointing errors. From both experimental and analytical work it can be concluded that the problem of the stringent link-budget can be solved effectively by application of beam-steering techniques. The second part treats wideband transmission methods and relevant baseband algorithms. The considered schemes include orthogonal frequency division multiplexing (OFDM), multi-carrier code division multiple access (MC-CDMA) and single carrier with frequency-domain equalization (SC-FDE), which are promising candidates for Gb/s wireless transmission. In particular, the optimal linear equalization in the frei quency domain and associated implementation issues such as synchronization and channel estimation are examined. Bit error rate (BER) expressions are derived to evaluate the transmission performance. Besides the linear equalization techniques, a low-complexity inter-symbol interference cancellation technique is proposed to achieve much better performance of code-spreading systems such as MC-CDMA and SC-FDE. Both theoretical analysis and simulations demonstrate that the proposed scheme offers great advantages as regards both complexity and performance. This makes it particularly suitable for 60-GHz applications in multipath environments. The third part treats the influence of quantization and RF imperfections on the considered transmission methods in the context of 60-GHz radios. First, expressions for the BER are derived and the influence of nonlinear distortions caused by the digital-to-analog converters, analog-to-digital converters and power amplifiers on the BER performance is examined. Next, the BER performance under the influence of phase noise and IQ imbalance is evaluated for the case that digital compensation techniques are applied in the receiver as well as for the case that such techniques are not applied. Finally, a baseline design of a low-cost Gb/s 60-GHz transceiver is presented. It is shown that, by application of beam-steering in combination with SC-FDE without advanced channel coding, a data rate in the order of 2 Gb/s can be achieved over a distance of 10 meters in a typical NLOS indoor scenario

Low-Noise Amplifier and Noise/Distortion Shaping Beamformer

The emergence of advanced technologies has increased the need for fast and efficient mobile communication that can facilitate transferring large amounts of data and simultaneously serve multiple users. Future wireless systems will rely on millimeter-wave frequencies, enabled by recent silicon hardware advancements. High-frequency millimeter-wave technology and low-noise receiver front ends and amplifiers are key for improved performance and energy efficiency. This thesis proposes two LNA topologies that offer wide input-power-matched bandwidths and low noise figures, eliminating the need for complex matching networks at the LNA input. These topologies use intrinsic feedback through gate-drain networks and/or the resistance of the SOI-transistor back-gate terminal to achieve the real part of the input impedance. The two LNAs are experimentally demonstrated with two 22-nm FDSOI LNAs. One LNA, matched with the assistance of the gate-drain network, exhibits a bandwidth ranging from 7.7-33.3 GHz, which is further improved to 6-38.7 GHz through the application of the back-gate-resistance method. The two LNAs have noise-figure minima of 1.8 and 1.9 dB, maximum gains of 14.7 and 15.6 dB, and maximum IP1dBs of -9.1 and -7.8 dBm while consuming 10 and 7.8 mW of power and occupying 0.04 and 0.03 mm^2 of active areas, respectively. This thesis also presents the first experimental demonstration of noise/distortion (ND) shaping beamformer. The NDs originating in the receiver itself are spatio-temporally shaped away from the beamformer region of support, thereby permitting their suppression by the beamformer. The demonstrator is a 24.3-28.7 GHz, 79.28 mW 4-port receiver for a 4-element antenna array implemented in 22-nm FDSOI CMOS. When shaping was enabled, the concept demonstrator provided average improvements to the NF and IP1dB of 1.6 dB and 2.25 dB, respectively (compared to a reference design), and achieved NF=2.6 dB and IP1dB=-18.7dBm while consuming 19.8 mW/channel