An Efficient Algorithm for Finding Dominant Trapping Sets of LDPC Codes

This paper presents an efficient algorithm for finding the dominant trapping sets of a low-density parity-check (LDPC) code. The algorithm can be used to estimate the error floor of LDPC codes or to be part of the apparatus to design LDPC codes with low error floors. For regular codes, the algorithm is initiated with a set of short cycles as the input. For irregular codes, in addition to short cycles, variable nodes with low degree and cycles with low approximate cycle extrinsic message degree (ACE) are also used as the initial inputs. The initial inputs are then expanded recursively to dominant trapping sets of increasing size. At the core of the algorithm lies the analysis of the graphical structure of dominant trapping sets and the relationship of such structures to short cycles, low-degree variable nodes and cycles with low ACE. The algorithm is universal in the sense that it can be used for an arbitrary graph and that it can be tailored to find other graphical objects, such as absorbing sets and Zyablov-Pinsker (ZP) trapping sets, known to dominate the performance of LDPC codes in the error floor region over different channels and for different iterative decoding algorithms. Simulation results on several LDPC codes demonstrate the accuracy and efficiency of the proposed algorithm. In particular, the algorithm is significantly faster than the existing search algorithms for dominant trapping sets

Structural Design and Analysis of Low-Density Parity-Check Codes and Systematic Repeat-Accumulate Codes

The discovery of two fundamental error-correcting code families, known as turbo codes and low-density parity-check (LDPC) codes, has led to a revolution in coding theory and to a paradigm shift from traditional algebraic codes towards modern graph-based codes that can be decoded by iterative message passing algorithms. From then on, it has become a focal point of research to develop powerful LDPC and turbo-like codes. Besides the classical domain of randomly constructed codes, an alternative and competitive line of research is concerned with highly structured LDPC and turbo-like codes based on combinatorial designs. Such codes are typically characterized by high code rates already at small to moderate code lengths and good code properties such as the avoidance of harmful 4-cycles in the code's factor graph. Furthermore, their structure can usually be exploited for an efficient implementation, in particular, they can be encoded with low complexity as opposed to random-like codes. Hence, these codes are suitable for high-speed applications such as magnetic recording or optical communication. This thesis greatly contributes to the field of structured LDPC codes and systematic repeat-accumulate (sRA) codes as a subclass of turbo-like codes by presenting new combinatorial construction techniques and algebraic methods for an improved code design. More specifically, novel and infinite families of high-rate structured LDPC codes and sRA codes are presented based on balanced incomplete block designs (BIBDs), which form a subclass of combinatorial designs. Besides of showing excellent error-correcting capabilites under iterative decoding, these codes can be implemented efficiently, since their inner structure enables low-complexity encoding and accelerated decoding algorithms. A further infinite series of structured LDPC codes is presented based on the notion of transversal designs, which form another subclass of combinatorial designs. By a proper configuration of these codes, they reveal an excellent decoding performance under iterative decoding, in particular, with very low error-floors. The approach for lowering these error-floors is threefold. First, a thorough analysis of the decoding failures is carried out, resulting in an extensive classification of so-called stopping sets and absorbing sets. These combinatorial entities are known to be the main cause of decoding failures in the error-floor region over the binary erasure channel (BEC) and additive white Gaussian noise (AWGN) channel, respectively. Second, the specific code structures are exploited in order to calculate conditions for the avoidance of the most harmful stopping and absorbing sets. Third, powerful design strategies are derived for the identification of those code instances with the best error-floor performances. The resulting codes can additionally be encoded with low complexity and thus are ideally suited for practical high-speed applications. Further investigations are carried out on the infinite family of structured LDPC codes based on finite geometries. It is known that these codes perform very well under iterative decoding and that their encoding can be achieved with low complexity. By combining the latest findings in the fields of finite geometries and combinatorial designs, we generate new theoretical insights about the decoding failures of such codes under iterative decoding. These examinations finally help to identify the geometric codes with the most beneficial error-correcting capabilities over the BEC

Efficient Information Reconciliation for Quantum Key Distribution = Reconciliación eficiente de información para la distribución cuántica de claves

Advances in modern cryptography for secret-key agreement are driving the development of new methods and techniques in key distillation. Most of these developments, focusing on information reconciliation and privacy amplification, are for the direct benefit of quantum key distribution (QKD). In this context, information reconciliation has historically been done using heavily interactive protocols, i.e. with a high number of channel communications, such as the well-known Cascade. In this work we show how modern coding techniques can improve the performance of these methods for information reconciliation in QKD. Here, we propose the use of low-density parity-check (LDPC) codes, since they are good both in efficiency and throughput. A price to pay, a priori, using LDPC codes is that good efficiency is only attained for very long codes and in a very narrow range of error rates. This forces to use several codes in cases when the error rate varies significantly in different uses of the channel, a common situation for instance in QKD. To overcome these problems, this study examines various techniques for adapting LDPC codes, thus reducing the number of codes needed to cover the target range of error rates. These techniques are also used to improve the average efficiency of short-length LDPC codes based on a feedback coding scheme. The importance of short codes lies in the fact that they can be used for high throughput hardware implementations. In a further advancement, a protocol is proposed that avoids the a priori error rate estimation required in other approaches. This blind protocol also brings interesting implications to the finite key analysis. Los avances en la criptografía moderna para el acuerdo de clave secreta están empujando el desarrollo de nuevos métodos y técnicas para la destilación de claves. La mayoría de estos desarrollos, centrados en la reconciliación de información y la amplificación de privacidad, proporcionan un beneficio directo para la distribución cuántica de claves (QKD). En este contexto, la reconciliación de información se ha realizado históricamente por medio de protocolos altamente interativos, es decir, con un alto número de comunicaciones, tal y como ocurre con el protocolo Cascade. En este trabajo mostramos cómo las técnicas de codificación modernas pueden mejorar el rendimiento de estos métodos para la reconciliación de información en QKD. Proponemos el uso de códigos low-density parity-check (LDPC), puesto que estos son buenos tanto en eficiencia como en tasa de corrección. Un precio a pagar, a priori, utilizando códigos LDPC es que una buena eficiencia sólo se alcanza para códigos muy largos y en un rango de error limitado. Este hecho nos obliga a utilizar varios códigos en aquellos casos en los que la tasa de error varía significativamente para distintos usos del canal, una situación común por ejemplo en QKD. Para superar estos problemas, en este trabajo analizamos varias técnicas para la adaptación de códigos LDPC, y así poder reducir el número de códigos necesarios para cubrir el rango de errores deseado. Estas técnicas son también utilizadas para mejorar la eficiencia promedio de códigos LDPC cortos en un esquema de codificación con retroalimentación o realimentación (mensaje de retorno). El interés de los códigos cortos reside en el vii hecho de que estos pueden ser utilizados para implementaciones hardware de alto rendimiento. En un avance posterior, proponemos un nuevo protocolo que evita la estimación inicial de la tasa de error, requerida en otras propuestas. Este protocolo ciego también nos brinda implicaciones interesantes en el análisis de clave finita

Compute-and-Forward Relay Networks with Asynchronous, Mobile, and Delay-Sensitive Users

We consider a wireless network consisting of multiple source nodes, a set of relays and a destination node. Suppose the sources transmit their messages simultaneously to the relays and the destination aims to decode all the messages. At the physical layer, a conventional approach would be for the relay to decode the individual message one at a time while treating rest of the messages as interference. Compute-and-forward is a novel strategy which attempts to turn the situation around by treating the interference as a constructive phenomenon. In compute-and-forward, each relay attempts to directly compute a combination of the transmitted messages and then forwards it to the destination. Upon receiving the combinations of messages from the relays, the destination can recover all the messages by solving the received equations. When identical lattice codes are employed at the sources, error correction to integer combination of messages is a viable option by exploiting the algebraic structure of lattice codes. Therefore, compute-and-forward with lattice codes enables the relay to manage interference and perform error correction concurrently. It is shown that compute-and-forward exhibits substantial improvement in the achievable rate compared with other state-of-the-art schemes for medium to high signal-to-noise ratio regime. Despite several results that show the excellent performance of compute-and-forward, there are still important challenges to overcome before we can utilize compute-and- forward in practice. Some important challenges include the assumptions of \perfect timing synchronization "and \quasi-static fading", since these assumptions rarely hold in realistic wireless channels. So far, there are no conclusive answers to whether compute-and-forward can still provide substantial gains even when these assumptions are removed. When lattice codewords are misaligned and mixed up, decoding integer combination of messages is not straightforward since the linearity of lattice codes is generally not invariant to time shift. When channel exhibits time selectivity, it brings challenges to compute-and-forward since the linearity of lattice codes does not suit the time varying nature of the channel. Another challenge comes from the emerging technologies for future 5G communication, e.g., autonomous driving and virtual reality, where low-latency communication with high reliability is necessary. In this regard, powerful short channel codes with reasonable encoding/decoding complexity are indispensable. Although there are fruitful results on designing short channel codes for point-to-point communication, studies on short code design specifically for compute-and-forward are rarely found. The objective of this dissertation is threefold. First, we study compute-and-forward with timing-asynchronous users. Second, we consider the problem of compute-and- forward over block-fading channels. Finally, the problem of compute-and-forward for low-latency communication is studied. Throughout the dissertation, the research methods and proposed remedies will center around the design of lattice codes in order to facilitate the use of compute-and-forward in the presence of these challenges

The Design of Efficiently-Encodable Rate-Compatible LDPC Codes

We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing over a wide range of rates and are suitable for usage in incremental redundancy hybrid-automatic repeat request (ARQ) systems. In addition, these codes are linear-time encodable with simple shift-register circuits. For a block length of 1200 bits the codes outperform optimized irregular LDPC codes and extended irregular repeat-accumulate (eIRA) codes for all puncturing rates 0.6~0.9 (base code performance is almost the same) and are particularly good at high puncturing rates where good puncturing performance has been previously difficult to achieve.Comment: Accepted subject to minor revision to IEEE Trans. on Com

Superposition Mapping & Related Coding Techniques

Since Shannon's landmark paper in 1948, it has been known that the capacity of a Gaussian channel can be achieved if and only if the channel outputs are Gaussian. In the low signal-to-noise ratio (SNR) regime, conventional mapping schemes suffice for approaching the Shannon limit, while in the high SNR regime, these mapping schemes, which produce uniformly distributed symbols, are insufficient to achieve the capacity. To solve this problem, researchers commonly resort to the technique of signal shaping that mends the symbol distribution, which is originally uniform, into a Gaussian-like one. Superposition mapping (SM) refers to a class of mapping techniques which use linear superposition to load binary digits onto finite-alphabet symbols that are suitable for waveform transmission. Different from conventional mapping schemes, the output symbols of a superposition mapper can easily be made Gaussian-like, which effectively eliminates the necessity of active signal shaping. For this reason, superposition mapping is of great interest for theoretical research as well as for practical implementations. It is an attractive alternative to signal shaping for approaching the channel capacity in the high SNR regime. This thesis aims to provide a deep insight into the principles of superposition mapping and to derive guidelines for systems adopting it. Particularly, the influence of power allocation to the system performance, both w.r.t the achievable power efficiency and supportable bandwidth efficiency, is made clear. Considerable effort is spent on finding code structures that are matched to SM. It is shown that currently prevalent code design concepts, which are mostly derived for coded transmission with bijective uniform mapping, do not really fit with superposition mapping, which is often non-bijective and nonuniform. As the main contribution, a novel coding strategy called low-density hybrid-check (LDHC) coding is proposed. LDHC codes are optimal and universally applicable for SM with arbitrary type of power allocation

The Design of Efficiently-Encodable Rate-Compatible LDPC Codes

We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing over a wide range of rates and are suitable for usage in incremental redundancy hybrid-automatic repeat request (ARQ) systems. In addition, these codes are linear-time encodable with simple shift-register circuits. For a block length of 1200 bits the codes outperform optimized irregular LDPC codes and extended irregular repeat-accumulate (eIRA) codes for all puncturing rates 0.6~0.9 (base code performance is almost the same) and are particularly good at high puncturing rates where good puncturing performance has been previously difficult to achieve

새로운 소실 채널을 위한 자기동형 군 복호기 및 부분 접속 복구 부호 및 일반화된 근 프로토그래프 LDPC 부호의 설계

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2019. 2. 노종선.In this dissertation, three main contributions are given asi) new two-stage automorphism group decoders (AGD) for cyclic codes in the erasure channel, ii) new constructions of binary and ternary locally repairable codes (LRCs) using cyclic codes and existing LRCs, and iii) new constructions of high-rate generalized root protograph (GRP) low-density parity-check (LDPC) codes for a nonergodic block interference and partially regular (PR) LDPC codes for follower noise jamming (FNJ), are considered. First, I propose a new two-stage AGD (TS-AGD) for cyclic codes in the erasure channel. Recently, error correcting codes in the erasure channel have drawn great attention for various applications such as distributed storage systems and wireless sensor networks, but many of their decoding algorithms are not practical because they have higher decoding complexity and longer delay. Thus, the AGD for cyclic codes in the erasure channel was introduced, which has good erasure decoding performance with low decoding complexity. In this research, I propose new TS-AGDs for cyclic codes in the erasure channel by modifying the parity check matrix and introducing the preprocessing stage to the AGD scheme. The proposed TS-AGD is analyzed for the perfect codes, BCH codes, and maximum distance separable (MDS) codes. Through numerical analysis, it is shown that the proposed decoding algorithm has good erasure decoding performance with lower decoding complexity than the conventional AGD. For some cyclic codes, it is shown that the proposed TS-AGD achieves the perfect decoding in the erasure channel, that is, the same decoding performance as the maximum likelihood (ML) decoder. For MDS codes, TS-AGDs with the expanded parity check matrix and the submatrix inversion are also proposed and analyzed. Second, I propose new constructions of binary and ternary LRCs using cyclic codes and existing two LRCs for distributed storage system. For a primitive work, new constructions of binary and ternary LRCs using cyclic codes and their concatenation are proposed. Some of proposed binary LRCs with Hamming weights 4, 5, and 6 are optimal in terms of the upper bounds. In addition, the similar method of the binary case is applied to construct the ternary LRCs with good parameters. Also, new constructions of binary LRCs with large Hamming distance and disjoint repair groups are proposed. The proposed binary linear LRCs constructed by using existing binary LRCs are optimal or near-optimal in terms of the bound with disjoint repair group. Last, I propose new constructions of high-rate GRP LDPC codes for a nonergodic block interference and anti-jamming PR LDPC codes for follower jamming. The proposed high-rate GRP LDPC codes are based on nonergodic two-state binary symmetric channel with block interference and Nakagami-$m$ block fading. In these channel environments, GRP LDPC codes have good performance approaching to the theoretical limit in the channel with one block interference, where their performance is shown by the channel threshold or the channel outage probability. In the proposed design, I find base matrices using the protograph extrinsic information transfer (PEXIT) algorithm. Also, the proposed new constructions of anti-jamming partially regular LDPC codes is based on follower jamming on the frequency-hopped spread spectrum (FHSS). For a channel environment, I suppose follower jamming with random dwell time and Rayleigh block fading environment with M-ary frequnecy shift keying (MFSK) modulation. For a coding perspective, an anti-jamming LDPC codes against follower jamming are introduced. In order to optimize the jamming environment, the partially regular structure and corresponding density evolution schemes are used. A series of simulations show that the proposed codes outperforms the 802.16e standard in the presence of follower noise jamming.이 논문에서는, i) 소실 채널에서 순환 부호의 새로운 이단 자기동형 군 복호기 , ii) 분산 저장 시스템을 위한 순환 부호 및 기존의 부분 접속 복구 부호(LRC)를 이용한 이진 혹은 삼진 부분 접속 복구 부호 설계법, 및 iii) 블록 간섭 환경을 위한 고부효율의 일반화된 근 프로토그래프(generalized root protograph, GRP) LDPC 부호 및 추적 재밍 환경을 위한 항재밍 부분 균일 (anti-jamming paritally regular, AJ-PR) LDPC 부호가 연구되었다. 첫번째로, 소실 채널에서 순환 부호의 새로운 이단 자기동형 군 복호기를 제안하였다. 최근 분산 저장 시스템 혹은 무선 센서 네트워크 등의 응용으로 인해 소실 채널에서의 오류 정정 부호 기법이 주목받고 있다. 그러나 많은 복호기 알고리즘은 높은 복호 복잡도 및 긴 지연으로 인해 실용적이지 못하다. 따라서 낮은 복호 복잡도 및 높은 성능을 보일 수 있는 순환 부호에서 이단 자기 동형 군 복호기가 제안되었다. 본 연구에서는 패리티 검사 행렬을 변형하고, 전처리 과정을 도입한 새로운 이단 자기동형 군 복호기를 제안한다. 제안한 복호기는 perfect 부호, BCH 부호 및 최대 거리 분리 (maximum distance separable, MDS) 부호에 대해서 분석되었다. 수치 분석을 통해, 제안된 복호 알고리즘은 기존의 자기 동형 군 복호기보다 낮은 복잡도를 보이며, 몇몇의 순환 부호 및 소실 채널에서 최대 우도 (maximal likelihood, ML)과 같은 수준의 성능임을 보인다. MDS 부호의 경우, 확장된 패리티검사 행렬 및 작은 크기의 행렬의 역연산을 활용하였을 경우의 성능을 분석한다. 두 번째로, 분산 저장 시스템을 위한 순환 부호 및 기존의 부분 접속 복구 부호 (LRC)를 이용한 이진 혹은 삼진 부분 접속 복구 부호 설계법을 제안하였다. 초기 연구로서, 순환 부호 및 연접을 활용한 이진 및 삼진 LRC 설계 기법이 연구되었다. 최소 해밍 거리가 4,5, 혹은 6인 제안된 이진 LRC 중 일부는 상한과 비교해 보았을 때 최적 설계임을 증명하였다. 또한, 비슷한 방법을 적용하여 좋은 파라미터의 삼진 LRC를 설계할 수 있었다. 그 외에 기존의 LRC를 활용하여 큰 해밍 거리의 새로운 LRC를 설계하는 방법을 제안하였다. 제안된 LRC는 분리된 복구 군 조건에서 최적이거나 최적에 가까운 값을 보였다. 마지막으로, GRP LDPC 부호는 Nakagami-$m$ 블록 페이딩 및 블록 간섭이 있는 두 상태의 이진 대칭 채널을 기반으로 한다. 이러한 채널 환경에서 GRP LDPC 부호는 하나의 블록 간섭이 발생했을 경우, 이론적 성능에 가까운 좋은 성능을 보여준다. 이러한 이론 값은 채널 문턱값이나 채널 outage 확률을 통해 검증할 수 있다. 제안된 설계에서는, 변형된 PEXIT 알고리즘을 활용하여 기초 행렬을 설계한다. 또한 AJ-PR LDPC 부호는 주파수 도약 환경에서 발생하는 추적 재밍이 있는 환경을 기반으로 한다. 채널 환경으로 MFSK 변복조 방식의 레일리 블록 페이딩 및 무작위한 지속 시간이 있는 재밍 환경을 가정한다. 이러한 재밍 환경으로 최적화하기 위해, 부분 균일 구조 및 해당되는 밀도 진화 (density evolution, DE) 기법이 활용된다. 여러 시뮬레이션 결과는 추적 재밍이 존재하는 환경에서 제안된 부호가 802.16e에 사용되었던 LDPC 부호보다 성능이 우수함을 보여준다.Contents Abstract Contents List of Tables List of Figures 1 INTRODUCTION 1.1 Background 1.2 Overview of Dissertation 1.3 Notations 2 Preliminaries 2.1 IED and AGD for Erasure Channel 2.1.1 Iterative Erasure Decoder 2.1.1 Automorphism Group Decoder 2.2. Binary Locally Repairable Codes for Distributed Storage System 2.2.1 Bounds and Optimalities of Binary LRCs 2.2.2 Existing Optimal Constructions of Binary LRCs 2.3 Channels with Block Interference and Jamming 2.3.1 Channels with Block Interference 2.3.2 Channels with Jamming with MFSK and FHSS Environment. 3 New Two-Stage Automorphism Group Decoders for Cyclic Codes in the Erasure Channel 3.1 Some Definitions 3.2 Modification of Parity Check Matrix and Two-Stage AGD 3.2.1 Modification of the Parity Check Matrix 3.2.2 A New Two-Stage AGD 3.2.3 Analysis of Modification Criteria for the Parity Check Matrix 3.2.4 Analysis of Decoding Complexity of TS-AGD 3.2.5 Numerical Analysis for Some Cyclic Codes 3.3 Construction of Parity Check Matrix and TS-AGD for Cyclic MDS Codes 3.3.1 Modification of Parity Check Matrix for Cyclic MDS Codes . 3.3.2 Proposed TS-AGD for Cyclic MDS Codes 3.3.3 Perfect Decoding by TS-AGD with Expanded Parity Check Matrix for Cyclic MDS Codes 3.3.4 TS-AGD with Submatrix Inversion for Cyclic MDS Codes . . 4 New Constructions of Binary and Ternary LRCs Using Cyclic Codes and Existing LRCs 4.1 Constructions of Binary LRCs Using Cyclic Codes 4.2 Constructions of Linear Ternary LRCs Using Cyclic Codes 4.3 Constructions of Binary LRCs with Disjoint Repair Groups Using Existing LRCs 4.4 New Constructions of Binary Linear LRCs with d ≥ 8 Using Existing LRCs 5 New Constructions of Generalized RP LDPC Codes for Block Interference and Partially Regular LDPC Codes for Follower Jamming 5.1 Generalized RP LDPC Codes for a Nonergodic BI 5.1.1 Minimum Blockwise Hamming Weight 5.1.2 Construction of GRP LDPC Codes 5.2 Asymptotic and Numerical Analyses of GRP LDPC Codes 5.2.1 Asymptotic Analysis of LDPC Codes 5.2.2 Numerical Analysis of Finite-Length LDPC Codes 5.3 Follower Noise Jamming with Fixed Scan Speed 5.4 Anti-Jamming Partially Regular LDPC Codes for Follower Noise Jamming 5.4.1 Simplified Channel Model and Corresponding Density Evolution 5.4.2 Construction of AJ-PR-LDPC Codes Based on DE 5.5 Numerical Analysis of AJ-PR LDPC Codes 6 Conclusion Abstract (In Korean)Docto

Advances in Modeling and Signal Processing for Bit-Patterned Magnetic Recording Channels with Written-In Errors

In the past perpendicular magnetic recording on continuous media has served as the storage mechanism for the hard-disk drive (HDD) industry, allowing for growth in areal densities approaching 0.5 Tb/in2. Under the current system design, further increases are limited by the superparamagnetic effect where the medium's thermal energy destabilizes the individual bit domains used for storage. In order to provide for future growth in the area of magnetic recording for disk drives, a number of various technology shifts have been proposed and are currently undergoing considerable research. One promising option involves switching to a discrete medium in the form of individual bit islands, termed bit-patterned magnetic recording (BPMR).When switching from a continuous to a discrete media, the problems encountered become substantial for every aspect of the hard-disk drive design. In this dissertation the complications in modeling and signal processing for bit-patterned magnetic recording are investigated where the write and read processes along with the channel characteristics present considerable challenges. For a target areal density of 4 Tb/in2, the storage process is hindered by media noise, two-dimensional (2D) intersymbol interference (ISI), electronics noise and written-in errors introduced during the write process. Thus there is a strong possibility that BPMR may prove intractable as a future HDD technology at high areal densities because the combined negative effects of the many error sources produces an environment where current signal processing techniques cannot accurately recover the stored data. The purpose here is to exploit advanced methods of detection and error correction to show that data can be effectively recovered from a BPMR channel in the presence of multiple error sources at high areal densities.First a practical model for the readback response of an individual island is established that is capable of representing its 2D nature with a Gaussian pulse. Various characteristics of the readback pulse are shown to emerge as it is subjected to the degradation of 2D media noise. The writing of the bits within a track is also investigated with an emphasis on the write process's ability to inject written-in errors in the data stream resulting from both a loss of synchronization of the write clock and the interaction of the local-scale magnetic fields under the influence of the applied write field.To facilitate data recovery in the presence of BPMR's major degradations, various detection and error-correction methods are utilized. For single-track equalization of the channel output, noise prediction is incorporated to assist detection with increased levels of media noise. With large detrimental amounts of 2D ISI and media noise present in the channel at high areal densities, a 2D approach known as multi-track detection is investigated where multiple tracks are sensed by the read heads and then used to extract information on the target track. For BPMR the output of the detector still possesses the uncorrected written-in errors. Powerful error-correction codes based on finite geometries are employed to help recover the original data stream. Increased error-correction is sought by utilizing two-fold EG codes in combination with a form of automorphism decoding known as auto-diversity. Modifications to the parity-check matrices of the error-correction codes are also investigated for the purpose of attempting more practical applications of the decoding algorithms based on belief propagation. Under the proposed techniques it is shown that effective data recovery is possible at an areal density of 4 Tb/in2 in the presence of all significant error sources except for insertions and deletions. Data recovery from the BPMR channel with insertions and deletions remains an open problem