Efficient 3D capacitance extraction solver using instantiable basis functions for VLSI interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 62-65).State-of-the-art capacitance extraction methods for Integrated Circuits (IC) involve scanning 2D cross-sections, and interpolating 2D capacitance values using a table lookup approach. This approach is fast and accurate for a large percentage of IC wires. It is however quite inaccurate for full 3D structures, such as crossing wires in adjacent metal layers. For such cases electrostatic field solvers are required. Unfortunately standard field solvers are inherently very time-consuming, making them completely impractical in typical IC design flows. Even fast matrix-vector product approaches (e.g., fastmultipole or precorrected FFT) are inefficient for these structures since they have a significant computational overhead and scale linearly with the number of conductors only for much larger structures with more than several hundreds of wires. In this talk we present therefore a new 3D extraction field solver that is extremely efficient in particular for the smaller scale extraction problem involving the ten to one hundred conductors in the 3D structures that cannot be handled by the 2D scanning and table look up approach. Because of highly restrictive design rules of the recent sub-micro to nano-scale IC technologies, smooth and regular charge distributions extracted from simple model structures can be stored beforehand as "templates" and instantiated and stretched to fit practical complicated cases as basis function building blocks. This "template-instantiated" strategy largely reduces the number of unknowns and computational time without additional overhead. Given that all basis functions are obtained by the same very few stretched templates, Galerkin coefficients can be readily computed from a mixture of analytical, numerical and table lookup approaches. Furthermore, given the low accuracy (i.e., 3%-5%) required by IC extraction and the specific aspect ratios and separations of wires on ICs, we have observed in our numerical experimentations that edge and corner charge singularities do not need to be included in our templates, hence reducing the complexity of our solver even further.by Yu-Chung Hsiao.S.M

Skin-Effect Loss Models for Time- and Frequency-Domain PEEC Solver

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Full-wave analysis of large conductor systems over substrate

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 137-145).Designers of high-performance integrated circuits are paying ever-increasing attention to minimizing problems associated with interconnects such as noise, signal delay, crosstalk, etc., many of which are caused by the presence of a conductive substrate. The severity of these problems increases as integrated circuit clock frequencies rise into the multiple gigahertz range. In this thesis, a simulation tool is presented for the extraction of full-wave interconnect impedances in the presence of a conducting substrate. The substrate effects are accounted for through the use of full-wave layered Green's functions in a mixed-potential integral equation (MPIE) formulation. Particularly, the choice of implementation for the layered Green's function kernels motivates the development of accelerated techniques for both their 3D volume and 2D surface integrations, where each integration type can be reduced to a sum of D line integrals. In addition, a set of high-order, frequency-independent basis functions is developed with the ability to parameterize the frequency-dependent nature of the solution space, hence reducing the number of unknowns required to capture the interconnects' frequency-variant behavior.(cont.) Moreover, a pre-corrected FFT acceleration technique, conventional for the treatment of scalar Green's function kernels, is extended in the solver to accommodate the dyadic Green's function kernels encountered in the substrate modeling problem. Overall, the integral-equation solver, combined with its numerous acceleration techniques, serves as a viable solution to full-wave substrate impedance extractions of large and complex interconnect structures.by Xin Hu.Ph.D

Full-wave Surface Integral Equation Method for Electromagnetic-circuit Simulation of Three-dimensional Interconnects in Layered Media

A new full-wave surface impedance integral equation method is presented for three-dimensional arbitrary-shaped interconnect parasitic extraction in layered media. Various new ways of applying voltage and current excitations for electromagnetic-circuit simulation are introduced. A new algorithm is proposed for matrix formation of electromagnetic-circuit simulation, low frequency solution and layered media so that it can be easily integrated to a Rao-Wilton-Glisson based method of moment code. Two mixed potential integral equation forms of the electric field integral equation are adapted along with the Michalski-Mosig formulations for layered kernels to model electromagnetic interactions of interconnects in layered media over a conducting substrate. The layered kernels are computed directly for controllable accuracy. The proposed methods are validated against existing methods for both electromagnetic and electromagnetic-circuit problems

Digitally driven microfabrication of 3D multilayer embedded electronic systems

The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality

Factors shaping the evolution of electronic documentation systems

The main goal is to prepare the space station technical and managerial structure for likely changes in the creation, capture, transfer, and utilization of knowledge. By anticipating advances, the design of Space Station Project (SSP) information systems can be tailored to facilitate a progression of increasingly sophisticated strategies as the space station evolves. Future generations of advanced information systems will use increases in power to deliver environmentally meaningful, contextually targeted, interconnected data (knowledge). The concept of a Knowledge Base Management System is emerging when the problem is focused on how information systems can perform such a conversion of raw data. Such a system would include traditional management functions for large space databases. Added artificial intelligence features might encompass co-existing knowledge representation schemes; effective control structures for deductive, plausible, and inductive reasoning; means for knowledge acquisition, refinement, and validation; explanation facilities; and dynamic human intervention. The major areas covered include: alternative knowledge representation approaches; advanced user interface capabilities; computer-supported cooperative work; the evolution of information system hardware; standardization, compatibility, and connectivity; and organizational impacts of information intensive environments

Microfluidics and Nanofluidics Handbook

The Microfluidics and Nanofluidics Handbook: Two-Volume Set comprehensively captures the cross-disciplinary breadth of the fields of micro- and nanofluidics, which encompass the biological sciences, chemistry, physics and engineering applications. To fill the knowledge gap between engineering and the basic sciences, the editors pulled together key individuals, well known in their respective areas, to author chapters that help graduate students, scientists, and practicing engineers understand the overall area of microfluidics and nanofluidics. Topics covered include Finite Volume Method for Numerical Simulation Lattice Boltzmann Method and Its Applications in Microfluidics Microparticle and Nanoparticle Manipulation Methane Solubility Enhancement in Water Confined to Nanoscale Pores Volume Two: Fabrication, Implementation, and Applications focuses on topics related to experimental and numerical methods. It also covers fabrication and applications in a variety of areas, from aerospace to biological systems. Reflecting the inherent nature of microfluidics and nanofluidics, the book includes as much interdisciplinary knowledge as possible. It provides the fundamental science background for newcomers and advanced techniques and concepts for experienced researchers and professionals

Liquid cooled micro-scale gradient system for magnetic resonance

Schaltbare magnetische Feldgradientspulen sind ein geeignetes Werkzeug für die Modulation der Kernspinpräzession in der gepulsten Kernspinresonanzspektroskopie und Bildgebung. Die Magnetresonanztomographie von mikroskopischen Proben benötigt starke, schnell schaltbare Magnetfeldgradienten, um diffusionsbedingte Artefakte zu unterdrücken, Suszeptibilitätseffekte abzuschwächen und um die Messzeit zu verkürzen. Verschiedene Techniken können eingesetzt werden, um eine hohe Gradientenintensität zu erreichen, wie zum Beispiel die Erhöhung der Stromstärke oder die Steigerung der Windungsdichte der Feldspule. Ein weiterer, geeigneter technischer Ansatz besteht darin, die Gradientenspulen näher an der Probe zu platzieren. Als Konsequenz wird aber die durch die Joule-Erwärmung verursachte Wärmeentwicklung zu einem zentralen Problem. In dieser Arbeit wird ein neuartiges Design, ein Mikroherstellungsprozess und eine Kernspin-Evaluierung eines Feldgradientenchips präsentiert. Die Gradientenspulen wurden besonders hoch miniaturisiert und durch den Einsatz von verbesserten und neuartigen Strukturierungsverfahren entwickelt. Zuerst wird ein Fertigungsverfahren zur Herstellung einer kompakten Hochfrequenzspule vorgestellt. Durch den Einsatz einer maskenlosen Rückseitenlithographie konnte die Prozesskomplexität reduziert werden. Dieses Verfahren wurde durch Tintenstrahldruck mit Nanopartikeln realisiert, wobei die gedruckten Strukturen selbst als lithographische Maske für die Herstellung einer galvanischen Form dienen. Somit werden die Seitenwände der galvanischen Form durch die gedruckte Seed-Schicht optimal selbst ausgerichtet. Dies ermöglichte eine anisotrope Galvanisierung, um eine höhere elektrische Leitfähigkeit der gedruckten Leiterbahnen zu erzielen. Aus den Erkenntnissen der ausgearbeiteten Herstellungsprozesse wurde ein optimiertes Spulendesign für ein-axiale sowie drei-axiale linearen Gradientenchips entwickelt. Die einachsige lineare $z$-Gradientenspule wurde mit der Stream-Function-Methode berechnet, wobei die Optimierung darauf abgestimmt wurde, eine minimale Verlustleistung zu erzielen. Die Gradientenspulen wurden auf zwei Doppellagen implementiert, die mittels Cu-Galvanik in Kombination mit fotodefinierbaren Trockenfilm-Laminaten aufgebracht wurden. Bei dem hier vorgestellten Herstellungsverfahren diente die erste Metallisierungschicht gleichzeitig dazu, Widerstands-Temperaturdetektoren zu integrieren. Um niederohmige Spulen zu realisieren wurde der Galvanisierungsprozess soweit angepasst, um eine hohe Schichtdicke zu erzielen. Die Chipstruktur beinhaltet ein aktives Kühlsystem, um dem Aufheizen der Spulen entgegenzuwirken. Thermographische Aufnahmen in Kombination mit den eingebetteten Temperatursensoren ermöglichen es, die Erhitzung der Spule zu analysieren, um die Strombelastbarkeit zu ermitteln. Die Gradientenspule wurde mit einer Hochfrequenz-Mikrospule in einer Flip-Chip-Konfiguration zusammengebaut, und mit diesem Aufbau wurde ein eindimensionales Kernspinexperiment durchgeführt. Es wurde eine Gradienteneffizienz von 3.15 $T\,m^{−1}\,A^{−1}$ bei einer Profillänge von 1.2 $mm$ erreicht