Design, processing and testing of LSI arrays hybrid microelectronics task

Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

NASA Tech Briefs Index, 1978

Approximately 601 announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Emphasis is placed on information considered likely to be transferrable across industrial, regional, or disciplinary lines. Subject matter covered includes: electronic components and circuits; electron systems; physical sciences; materials; life sciences; mechanics; machinery; fabrication technology; and mathematics and information sciences

Feasibility of remotely manipulated welding in space. A step in the development of novel joining technologies

In order to establish permanent human presence in space technologies of constructing and repairing space stations and other space structures must be developed. Most construction jobs are performed on earth and the fabricated modules will then be delivered to space by the Space Shuttle. Only limited final assembly jobs, which are primarily mechanical fastening, will be performed on site in space. Such fabrication plans, however, limit the designs of these structures, because each module must fit inside the transport vehicle and must withstand launching stresses which are considerably high. Large-scale utilization of space necessitates more extensive construction work on site. Furthermore, continuous operations of space stations and other structures require maintenance and repairs of structural components as well as of tools and equipment on these space structures. Metal joining technologies, and especially high-quality welding, in space need developing

Index to 1981 NASA Tech Briefs, volume 6, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1981 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Electrical termination techniques

A technical review of high reliability electrical terminations for electronic equipment was made. Seven techniques were selected from this review for further investigation, experimental work, and preliminary testing. From the preliminary test results, four techniques were selected for final testing and evaluation. These four were: (1) induction soldering, (2) wire wrap, (3) percussive arc welding, and (4) resistance welding. Of these four, induction soldering was selected as the best technique in terms of minimizing operator errors, controlling temperature and time, minimizing joint contamination, and ultimately producing a reliable, uniform, and reusable electrical termination

Development and Integration of MEMS Based Inductive Sensors

Inductive sensors are one of the most widely used sensors especially in automotive. However, with the current PCB manufacture process, the large size of the sensor limits its usage in different applications. In this thesis, a novel method of fabricating bi-layer copper micro inductive sensor is demonstrated to solve the size issue. The two coil layers were built by UV LIGA process respectively, and a polyimide insulation film sandwiched in between. At the beginning, seeding layer was deposited on the substrate as electrode, and then the copper coil layer was created through electroplating in the patterned micromold. The coil was prepared after striping off the seeding layer and micromold. Lately, the fabricated coil chips, ASIC, and capacitors were integrated together through PCB board by using wire bonding and SMT process. A reliable procedure of building robust micro inductive sensor was developed with the consideration of future mass production possibility. The good test results compared with simulation proved the feasibility of developing and fabricating miniaturized micro inductive sensor

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated

Fabrication feasibility study of a 20 watt per pound solar cell array Final report, 22 Feb. - Dec. 1965

Feasibility of large deployable solar photovoltaic cell array for electric propulsion syste

Study to develop process controls for line certification on hybrid microcircuits Final report, Nov. 1970 - Feb. 1971

Basic process steps for fabrication of thick or thin film microcircuits for NASA us

The Detection of Defects in a Niobium Tri-layer Process

Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections