4 research outputs found
Bridging the Gap between Programming Languages and Hardware Weak Memory Models
We develop a new intermediate weak memory model, IMM, as a way of
modularizing the proofs of correctness of compilation from concurrent
programming languages with weak memory consistency semantics to mainstream
multi-core architectures, such as POWER and ARM. We use IMM to prove the
correctness of compilation from the promising semantics of Kang et al. to POWER
(thereby correcting and improving their result) and ARMv7, as well as to the
recently revised ARMv8 model. Our results are mechanized in Coq, and to the
best of our knowledge, these are the first machine-verified compilation
correctness results for models that are weaker than x86-TSO
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores
Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing with non-volatile memory. We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically validated our formalisation of the consistency semantics of these additional features and their subtle interactions by extensive testing on different Intel-x86 implementations
Promising Compilation to ARMv8 POP
We prove the correctness of compilation of relaxed memory accesses and release-acquire fences from the "promising" semantics of [Kang et al. POPL\u2717] to the ARMv8 POP machine of [Flur et al. POPL\u2716]. The proof is highly non-trivial because both the ARMv8 POP and the promising semantics provide some extremely weak consistency guarantees for normal memory accesses; however, they do so in rather different ways. Our proof of compilation correctness to ARMv8 POP strengthens the results of the Kang et al., who only proved the correctness of compilation to x86-TSO and Power, which are much simpler in comparison to ARMv8 POP
Recommended from our members
The Semantics of Multicopy Atomic ARMv8 and RISC-V
Previous work has established precise operational concurrency models
for Power and ARMv8, in an abstract micro-architectural style based on
detailed discussion with IBM and ARM staff and extensive hardware
testing. To account for the precise architectural behaviour these
models are complex. This thesis aims to provide a better understanding
for the relaxed memory concurrency models of the architectures ARMv8,
RISC-V, and (to a lesser degree) Power.
Power and early versions of ARMv8 have non-multicopy-atomic (non-MCA)
concurrency models. This thesis provides abstraction results for
these, including a more abstract non-MCA ARMv8 storage subsystem
model, and characterisations of the behaviour of mixed-size Power and
non-MCA ARMv8 programs when using barriers or release/acquire
instructions for all memory accesses, with respect to notions of
Sequential Consistency for mixed-size programs.
During the course of this PhD project, and partly due to our extended
collaboration with ARM, ARM have shifted to a much simplified
multicopy-atomic concurrency architecture that also includes a formal
axiomatic concurrency model. We develop a correspondingly simplified
operational model based on the previous non-MCA models, and, as the
main result of this thesis, prove equivalence between the simplified
operational and the reference axiomatic model.
We have also been actively involved in the RISC-V Memory Model Task
Group. RISC-V has adopted a multicopy atomic model closely following
that of ARMv8, but which incorporates some changes motivated by issues
raised in our operational modelling of ARMv8. We develop an adapted
RISC-V operational concurrency model that is now part of the official
architecture documentation.
Finally, in order to give a simpler explanation of the MCA ARMv8 and
RISC-V concurrency models for programmers, we develop an equivalent
operational concurrency model in a different style. The
\promisingarmriscv model, based on the C11 Promising model, gives up
the micro-architectural intuition the other operational models offer
in favour of providing a more abstract model. We prove it equivalent
to the MCA ARMv8 and RISC-V axiomatic models in Coq.This work was funded by a Computer Laboratory and Qualcomm Premium Studentship, an EPSRC and Arm Ltd. Industrial CASE Studentship (grant no. EP/L505389/1), and the EPSRC Programme Grant “REMS: Rigorous Engineering for Mainstream Systems” (grant no. EP/K008528/1)