Controlled growth of CH3_3NH3_3PbI3_3 nanowires in arrays of open nanofluidic channels

Spatial positioning of nanocrystal building blocks on a solid surface is a prerequisite for assembling individual nanoparticles into functional devices. Here, we report on the graphoepitaxial liquid-solid growth of nanowires of the photovoltaic compound CH$_3$NH$_3$PbI$_3$ in open nanofluidic channels. The guided growth, visualized in real-time with a simple optical microscope, undergoes through a metastable solvatomorph formation in polar aprotic solvents. The presently discovered crystallization leads to the fabrication of mm2-sized surfaces composed of perovskite nanowires having controlled sizes, cross-sectional shapes, aspect ratios and orientation which have not been achieved thus far by other deposition methods. The automation of this general strategy paves the way towards fabrication of wafer-scale perovskite nanowire thin films well-suited for various optoelectronic devices, e.g. solar cells, lasers, light-emitting diodes and photodetectors

Nanowire nanocomputer as a finite-state machine

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly-organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine (nanoFSM). The system was fabricated using a design- oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoFSM through modular design employing a multi-tile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoFSM integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive inter-tile and intra-tile communication that exhibits rigorous input/output (I/O) matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a FSM or computer. The programmable multi-tile circuit was also re-programmed to a functionally-distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our new design-oriented deterministic methodology to yield more extensive multi-tile systems, suggest that proposed general-purpose nanocomputers can be realized in the near future.Chemistry and Chemical BiologyEngineering and Applied Science

Study of Local Power Dissipation in Ultrascaled Silicon Nanowire FETs

The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel

A versatile synthesis method of dendrites-free segmented nanowires with a precise size control

We report an innovative strategy to obtain cylindrical nanowires combining well established and low-cost bottom-up methods such as template-assisted nanowires synthesis and electrodeposition process. This approach allows the growth of single-layer or multi-segmented nanowires with precise control over their length (from few nanometers to several micrometers). The employed techniques give rise to branched pores at the bottom of the templates and consequently dendrites at the end of the nanowires. With our method, these undesired features are easily removed from the nanowires by a selective chemical etching. This is crucial for magnetic characterizations where such non-homogeneous branches may introduce undesired features into the final magnetic response. The obtained structures show extremely narrow distributions in diameter and length, improved robustness and high-yield, making this versatile approach strongly compatible with large scale production at an industrial level. Finally, we show the possibility to tune accurately the size of the nanostructures and consequently provide an easy control over the magnetic properties of these nanostructures

Effects of substrate annealing on the gold-catalyzed growth of ZnO nanostructures

The effects of thermal substrate pretreatment on the growth of Au-catalyzed ZnO nanostructures by pulsed laser deposition are investigated. C-plane sapphire substrates are annealed prior to deposition of a thin Au layer. Subsequent ZnO growths on substrates annealed above 1,200°C resulted in a high density of nanosheets and nanowires, whereas lower temperatures led to low nanostructure densities. Separate Au film annealing experiments at 700°C showed little variation in the size and density of the Au catalyst droplets with substrate annealing temperature. The observed variation in the density of nanostructures is attributed to the number of surface nucleation sites on the substrate, leading to a competition between nucleation promoted by the Au catalyst and surface nucleation sites on the rougher surfaces annealed below 1,200°C

Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?

Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation

Electrothermal simulations of Si and III-V nanowire field effect transistors: A non-equilibrium Green's function study

Electro-thermal simulations in ultrascaled Si and InGaAs nanowire field effect transistors have been carried out. Devices with 2.2 × 2.2 nm2 and 3.6 × 3.6 nm2 cross-sections have been investigated. All the standard phonon scattering mechanisms for Si and InGaAs such as optical, polar optical (only for InGaAs), and acoustic phonon mechanisms have been considered. The Non-Equilibrium Green's Function formalism in concomitance with a renormalised 3D heat equation has been used to investigate the effect of self-heating. In addition, locally resolved electron power dissipation and temperature profiles have been extracted. The simulations showed that the heat dissipated inside the transistor increases as the nanowire cross-section decreases. It is also demonstrated that the commonly assumed Joule-heat dissipation overestimates the power dissipated in the transistors studied. It was found that in comparison with standard scattering simulations, electrothermal simulations caused a 72% and 85% decrease in the current in 2.2 × 2.2 nm2 cross-section Si and InGaAs core NanoWire Field Effect Transistors , respectively, when compared with ballistic simulations. The corresponding decrease for scattering without self-heating was 45% and 70% respectively

Synthesis and Optimization of Switching Nanoarrays

In this paper, we study implementation of Boolean functions with crossbar nanoarrays where each crosspoint behaves as a switch. This study has two main parts “formulation” and “optimization”. In the first part of formulation, we investigate nanoarray based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second part of optimization, we focus on four-terminal switch based implementations; we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E76