Process Mining of Programmable Logic Controllers: Input/Output Event Logs

This paper presents an approach to model an unknown Ladder Logic based Programmable Logic Controller (PLC) program consisting of Boolean logic and counters using Process Mining techniques. First, we tap the inputs and outputs of a PLC to create a data flow log. Second, we propose a method to translate the obtained data flow log to an event log suitable for Process Mining. In a third step, we propose a hybrid Petri net (PN) and neural network approach to approximate the logic of the actual underlying PLC program. We demonstrate the applicability of our proposed approach on a case study with three simulated scenarios

Enhancing declarative process models with DMN decision logic

Modeling dynamic, human-centric, non-standardized and knowledge-intensive business processes with imperative process modeling approaches is very challenging. Declarative process modeling approaches are more appropriate for these processes, as they offer the run-time flexibility typically required in these cases. However, by means of a realistic healthcare process that falls in the aforementioned category, we demonstrate in this paper that current declarative approaches do not incorporate all the details needed. More specifically, they lack a way to model decision logic, which is important when attempting to fully capture these processes. We propose a new declarative language, Declare-R-DMN, which combines the declarative process modeling language Declare-R with the newly adopted OMG standard Decision Model and Notation. Aside from supporting the functionality of both languages, Declare-R-DMN also creates bridges between them. We will show that using this language results in process models that encapsulate much more knowledge, while still offering the same flexibility

Variation aware analysis of bridging fault testing

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drive strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality

On a coalgebraic view on Logic

In this paper we present methods of transition from one perspective on logic to others, and apply this in particular to obtain a coalgebraic presentation of logic. The central ingredient in this process is to view consequence relations as morphisms in a category

Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations

The Problem of Analogical Inference in Inductive Logic

We consider one problem that was largely left open by Rudolf Carnap in his work on inductive logic, the problem of analogical inference. After discussing some previous attempts to solve this problem, we propose a new solution that is based on the ideas of Bruno de Finetti on probabilistic symmetries. We explain how our new inductive logic can be developed within the Carnapian paradigm of inductive logic-deriving an inductive rule from a set of simple postulates about the observational process-and discuss some of its properties.Comment: In Proceedings TARK 2015, arXiv:1606.0729

Model Checking Dynamic-Epistemic Spatial Logic

In this paper we focus on Dynamic Spatial Logic, the extension of Hennessy-Milner logic with the parallel operator. We develop a sound complete Hilbert-style axiomatic system for it comprehending the behavior of spatial operators in relation with dynamic/temporal ones. Underpining on a new congruence we define over the class of processes - the structural bisimulation - we prove the finite model property for this logic that provides the decidability for satisfiability, validity and model checking against process semantics. Eventualy we propose algorithms for validity, satisfiability and model checking