Instrument for determining coincidence and elapse time between independent sources of random sequential events

An instrument that receives pulses from a primary external source and one or more secondary external sources and determines when there is coincidence between the primary and one of the secondary sources is described. The instrument generates a finite time window (coincidence aperture) during which coincidence is defined to have occurred. The time intervals between coincidence apertures in which coincidences occur are measured

A programmable integrated power supply for the electrostatic-drive micromotor

A 6-phase bipolarized, high-voltage power supply with rectangular pulse shape has been designed to study the special operational characteristics of various electrostatic-drive micromotors. In particular the design powers the variable-capacitance side-drive micromotor. This power supply provides variable frequency, variable voltage, and variable duty-cycle control. Simulation has been used extensively in the design and design verification. The bipolarization (dual voltage polarity) of each pair of the phases reduces physical clamping of the rotor to the electrical shield beneath it. Thus, bipolarization of the voltage supplied to the stator nodes reduces charge build-up on the rotor. The output frequency range varying from 1Hz to 40KHz has been achieved. This supply frequency range corresponds to motor rotational speed range of 5rpm to 200Krpm, for a micromotor with 12 stator poles and 8 rotor poles (3:2 architec-ture). The voltage amplitudes of all six phases can be varied from 20 to 200Volts. The duty cycle of each phase can be changed by means of a parallel register. The output with variable duty cycle has been obtained, changing from 50% non-overlapping to 33% overlapping. The power supply with 6-phase bipolarized output, variable frequency, and variable voltage output has been constructed with prototyping wire wrap boards, and assembled in a card cage. The power supply is shown to meet the design specification

High Performance Low Power Dual Edge Triggered Static D Flip-Flop

In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence require lesser number of transistors and thus requires lesser overall silicon area.DOI:http://dx.doi.org/10.11591/ijece.v3i5.316

The first experimental flight package of an advanced telemetry system with adaptive capability Technical summary report, 1 Jul. 1963 - 15 Feb. 1965

Mechanical design, and environmental and functional testing of advanced telemetry system flight package with adaptive capabilit

Adaptive system and method for signal generation Patent

Adaptive signal generating system and logic circuits for satellite television system

Analog, hybrid, and digital simulation

Analog, hybrid, and digital computerized simulation technique

Atomic hydrogen maser for space vehicle application, phase 1 Final report, 1 Mar. 1966 - 31 Mar. 1968

Design and development of atomic hydrogen maser for space vehicle applicatio

Apollo experience report. Guidance and control systems: Orbital rate drive electronics for the Apollo command module and lunar module

A brief record of the development and use of the orbital-rate-drive assembly in the Apollo Program is presented. This device was procured as government-furnished equipment and was used on both the lunar module and the command module. Reviews of design, development, procurement, and flight experience are included

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly. Therefore, proposed a novel particle swarm based ADPLL (PS-ADPLL) with Coordinate Rotation Digital Computer (CORDIC) algorithm to attain the lock state of the ADPLL for the low-frequency applications. In the proposed architecture, the D flip-flop matches the frequency and the phase of the output and reference pulses and produces an error signals up and down signal. The up/down counter removes the higher frequency part and produces a carry and the borrow signal. These carry and borrow signals are then fed into the increment decrement counters to produce the output signal matching the frequency of the reference signal. However, the time delay is increased for low-frequency applications, which is critical for the lock state. So, the delay line length is calculated by the CORDIC algorithm and is optimized by the particle swarm activated in the phase detector to match the output pulse with the reference pulse and make ADPLL into a locked state. The presented PS-ADPLL is tested in FPGA. Furthermore, the performance parameters are evaluated and compared with other current techniques to calculate the improvement score