21 research outputs found

    Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework

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    © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Photonic interconnects are a promising solution for the so-called communication bottleneck in current Chip Multiprocessor (CMPs) architectures. This technology presents an inherent low-latency and power consumption almost independent of communication distance, which are really desirable features in future Networks on Chip for next CMPs generations. However, since nanophotonic technology is still growing and therefore in an immature state, current simulators of detailed systems may not provide accurate models of photonic components. In this context, non-representative results are obtained when unaccurate photonic models are assumed. This paper summarizes all of the components that conform a fully operative photonic NoC and presents their current state of the art. Moreover, we evaluate a realistic photonic network that consists of two photonic rings and a token-based arbitration mechanism and compare it against a non-realistic model. In addition, both realistic and non-realistic schemes are valuated under different configurations varying the number of wavelengths that photonic waveguides employ. The experimental results show that the non-realistic NoC presents up 6× network latency deviation with respect to the accurate model. This deviation is translated into a performance deviation higher than 10% in several applications studied, which demonstrates the importance of accurate models when simulating current technologies under development like nanophotonics. Finally, a power consumption model of the realistic photonic network is presented. The results show that the overall photonic network power consumption grows with the number of wavelengths per waveguide since the number of required modulators and receivers becomes higher. In this way, the proposed realistic photonic network, which employs only two wavelengths for arbitration and destination selection tasks, increases its power consumption up to 3%, so network designs with more complex arbitration mechanisms must take into account the impact of the number of wavelengths on the power consumption.This work was supported by the Spanish Ministerio de Economía y Competitividad (MINECO) and by Plan E funds under Grant TIN2015-66972-C5-1-R and the ExaNest project, funded by the European Union’s Horizon 2020 research andinnovation programme under grant agreement No 671553.Puche Lara, J.; Lechago Buendía, S.; Petit Martí, SV.; Gómez Requena, ME.; Sahuquillo Borrás, J. (2016). Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework. IEEE. https://doi.org/10.1109/HPCSim.2016.756836

    Implementation of SOI-Based Rib Waveguide for High-Speed Optical Interconnect

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    Silicon based photonics have generated strong interest in recent years, mainly in optical waveguide interconnects for microelectronic circuits. This paper presents a single mode condition (SMC) of SOI-based rib waveguide for high-speed Optical Interconnect (OI) implementation at a circuit level. In OptiBPM, a correlation analysis between two parameters, etched rib thickness (r) and effective index (neff) was investigated to identify the effects of width (W) on the rib waveguide. The waveguide performance of the OI links such as output power, propagation loss and propagation delay was recorded based on OptiSPICE simulation. A wavelength (λ) of 1550 nm has the advantages of low power loss and delay which makes it reliable for high-speed OI applications

    Towards zero latency photonic switching in shared memory networks

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    Photonic networks-on-chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper we explore techniques which intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for a signi cant proportion of memory transactions. We then show how this technique can be applied to multiple-socket shared memory systems with low latency and energy consumption penalties. Finally, we present ideas and initial results to demonstrate that cache miss prediction could be used to set up photonic circuits for more complex memory transactions and main memory accesses

    МЕТАЛЛИЧЕСКИЕ НАНОПЛЕНКИ НА МОНОКРИСТАЛЛИЧЕСКОМ КРЕМНИИ: РОСТ, СВОЙСТВА И ПРИМЕНЕНИЕ

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    The metal–silicon thin−film system is not isostructural and furthermore exhibits pronounced interdiffusion and chemical reactions. Therefore the growth of metallic films on silicon leads to a high concentration of defects in the film, especially at its substrate interface. The material also contains stress and a transition layer consisting of melts or compounds (silicides).We have considered theoretical viewpoints and reviewed experimental data on the growth and properties of metallic nanofilms (including multilayered ones) on silicon, and also provided a brief review of their applications. The films consist either of atomic−sized, quabquantum sized and quantum sized layers. We have suggested a low temperature film growth technology based on freezing growing layers during deposition by maintaining a low temperature of the substrate and using an atomic beam with a reduced heat power. The technology uses a specially shaped deposition system in which the distance between the source and the substrate is comparable to their size or smaller. Furthermore, we use a special time sequence of deposition that provides for a reduced substrate surface temperature due to greater intervals between deposition pulses. This growth method of atomically thin films and multilayered nanofilms excludes interdiffusion between the layers, reduces three−dimensional growth rate and relatively increases lateral layer growth rate.Тонкопленочная система металл — кремний является неизоструктурной и, кроме того, характеризуется ярко выраженными процессами взаимодиффузии и химическими реакциями. Поэтому рост металлических нанопленок на кремнии сопровождается высоким уровнем дефектности пленки, особенно ее границы раздела с подложкой. Также присутствуют напряжения и образуется переходный слой, состоящий из сплавов или соединений (силицидов). Рассмотрены теоретические представления и дан обзор экспериментальных результатов по росту и свойствам металлических нанопленок (включая многослойные) на кремнии, а также краткий обзор их применения. Пленки состоят как из атомно−тонких или субквантово−размерных, так и из квантово−размерных слоев. Предложен процесс низкотемпературного роста пленки, основанный на замораживании растущих слоев в процессе осаждения, путем поддержания пониженной температуры подложки и использования атомного пучка с пониженной тепловой мощностью. В этом процессе использована специальная геометрия системы осаждения, в которой расстояние между источником и подложкой сопоставимо или меньше их размеров. Кроме того, применена временнáя последовательность осаждения, которая обеспечивает поддержание пониженной температуры поверхности подложки за счет длительной выдержки между порциями осаждения. Такой рост атомно−тонких пленок и многослойных нанопленок предотвращает взаимодиффузию между слоями, ослабляет трехмерный рост и усиливает по отношению к этим процессам латеральный слоевой рост

    Exploiting Properties of CMP Cache Traffic in Designing Hybrid Packet/Circuit Switched NoCs

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    Chip multiprocessors with few to tens of processing cores are already commercially available. Increased scaling of technology is making it feasible to integrate even more cores on a single chip. Providing the cores with fast access to data is vital to overall system performance. When a core requires access to a piece of data, the core's private cache memory is searched first. If a miss occurs, the data is looked up in the next level(s) of the memory hierarchy, where often one or more levels of cache are shared between two or more cores. Communication between the cores and the slices of the on-chip shared cache is carried through the network-on-chip(NoC). Interestingly, the cache and NoC mutually affect the operation of each other; communication over the NoC affects the access latency of cache data, while the cache organization generates the coherence and data messages, thus affecting the communication patterns and latency over the NoC. This thesis considers hybrid packet/circuit switched NoCs, i.e., packet switched NoCs enhanced with the ability to configure circuits. The communication and performance benefit that come from using circuits is predicated on amortizing the time cost incurred for configuring the circuits. To address this challenge, NoC designs are proposed that take advantage of properties of the cache traffic, namely temporal locality and predictability, to amortize or hide the circuit configuration time cost. First, a coarse-grained circuit configuration policy is proposed that exploits the temporal locality in the cache traffic to periodically configure circuits for the heavily communicating nodes. This allows the design of a locality-aware cache that promotes temporal communication locality through data placement, while designing suitable data replacement and migration policies. Next, a fine-grained configuration policy, called Déjà Vu switching, is proposed for leveraging predictability of data messages by initiating a circuit configuration as soon as a cache hit is detected and before the data becomes available. Its benefit is demonstrated for saving interconnect energy in multi-plane NoCs. Finally, a more proactive configuration policy is proposed for fast caches, where circuit reservations are initiated by request messages, which can greatly improve communication latency and system performance

    Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

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    In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits
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