Path Delay Test Through Memory Arrays

Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced by scan cells, due to the area cost and the timing-critical nature of many of the paths into and out of memories. Thus, bits in a memory array can be considered non-scan storage elements. Test methods such as memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these tests aren’t sufficient to test the paths through the memory arrays. During structural (scan) test generation, memory arrays are treated as “black boxes” or memory arrays are bypassed to a known value. Black boxes decrease coverage loss while bypassing increases chip area and delay. Path delay test through memory arrays is proposed using pseudo functional test (PFT) with K Longest Paths Per Gate (KLPG). In this technique, any longest path that is captured into a non-scan cell (including a memory cell) is propagated to a scan cell. The propagation of the captured value from non-scan cell to scan cell occurs during low-speed clock cycles. In this work, we assume that only one extra coda cycle is sufficient to propagate the captured value to a scan cell. This is true if the output of the memory feeds combinational logic that in turn feeds scan cells. When we want to launch a transition from a memory output, different values are written into different address locations and the address is toggled between the locations. The ATPG writes the different values into the memory cells during the preamble cycles. In the case of launching a transition out of a non-scan cell, the cell must be written with an initial value during the preamble cycles, and the next value set on the non-scan cell input. Thus, it is possible to capture and launch transitions into and from memory and non-scan cells and thus test the path delay of the longest paths into and out of memory and non-scan cells

Efficient Path Delay Test Generation with Boolean Satisfiability

This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

Optimization of Pseudo Functional Path Delay Test Through Embedded Memories

Traditional automatic test pattern generation achieves high coverage of logic faults in integrated circuits. Automatic test of embedded memory arrays uses built-in self-test. Testing the memories and logic separately does not fully test the critical timing paths that go into or out of memories. Prior research has developed algorithms and software to test the longest paths into and out of embedded memories. However, in this prior work, the test generation time increased superlinearly with memory size. This is contrary to the intuition that the time should rise approximately linearly with memory size. This behavior limits the algorithm to circuits with relatively small memories. The focus of this research is to analyze the time complexity of the algorithm and propose changes to reduce the time required to test circuits with large memories. We use our prior work on pseudo functional K longest path per gate test generation, and the benchmark circuits with embedded memories developed in the prior work. Since the cells within a memory array are not scan cells, a value that is captured in a memory cell must be moved to a scan cell using low-speed coda cycles. This approach will also support the test of any non-scan flip-flop or latch, in addition to embedded memory arrays. In addition to testing the critical timing paths, testing through memories eliminates the logic “shadows” around the memory where faults cannot be tested. In this research our complexity analysis has identified the reason for the superlinear increase in test generation time with larger memories and verified this analysis with experimental results. We have also developed and implemented several heuristics to increase performance, with experimental results. This research also identifies the major algorithm changes required to further increase performance

Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time

Nouvelle technique de test de type délai plus robuste à la variation d'impédance du réseau de distribution d'alimentation

De nos jours, le test de balayage à vitesse nominale (SBAST, Scan Based at-Speed Testing) est l’approche de test de type délai la plus dominante. Ce type de test vient avec certains inconvénients, comme le bruit de tension d’alimentation (PSN, Power Supply Noise) produit pendant le mode test, qui diffère de celui induit pendant le mode fonctionnel. Quelques techniques de test de type SBAST ont été développées pour réduire cette chute de tension. Mais un aspect particulier a été négligé dans la littérature, à savoir l’impact de la variation d’impédance du réseau de distribution d’alimentation (PDN, Power Delivery Network) sur les tests de type délai. Ce projet de maîtrise présente une nouvelle technique de test SBAST, nommée (OCAS, One Clock Alternated Shift) pour minimiser l’impact potentiel de la variation d’impédance du réseau de distribution d’alimentation. La stratégie derrière cette nouvelle technique est d’imiter autant que possible le signal d’horloge du mode fonctionnel. Le but de cette imitation est d’obtenir des conditions de distribution d’alimentation similaires à celle du mode fonctionnel pour protéger le circuit en mode test contre les variations de Vdd dues aux variations d’impédance. Comme cas d’étude, nous considérons la variation d’impédance du PDN qui peut se produire avec les circuits intégrés 3D avec la variation du nombre de puces du circuit sous test (CUT, Circuit Under Test). Les résultats des simulations HSPICE montrent que la technique OCAS est moins sensible à une telle variation d’impédance et qu’elle surpasse les principales techniques existantes de SBAST. De plus, les résultats de la couverture des pannes de transition de la technique OCAS obtenue avec les outils (ATPG, Automatic Test Pattern Generation) sont fort acceptables. Cependant, le nombre de vecteurs de test nécessaires pour y parvenir sont plus élevés, en raison des limitations de ces outils

Émulation et comparaison du mode test et du mode fonctionnel des circuits intégrés à horloges multiples

Ce projet de maîtrise s’intéresse à la représentativité du test de balayage à vitesse nominale (SBAST : Scan based at-speed test) versus le mode fonctionnel en termes de délais et de bruit sur l’alimentation. Dans la littérature, les efforts déployés pour vérifier si le mode test est représentatif du mode fonctionnel ont porté presqu’exclusivement sur le mode test, le mode fonctionnel étant considéré comme un point de référence stable. À partir d’expérimentations préliminaires (Thibeault and Larche 2012), on a remarqué que le mode fonctionnel à multiples domaines d’horloge amène l’apparition de fluctuations indésirables appelées produits d’intermodulation (PIMs), jusqu’ici inexplorés dans ce contexte. Un des objectifs de cette recherche a donc porté sur l’étude de l’impact des PIMs sur les délais de propagation et sur la tension d’alimentation. Afin d’atteindre les objectifs de recherche, une plateforme expérimentale a été mise en place. Cette plateforme comprend un testeur et un circuit sous test (CUT). Du même coup, nous avons étudié l’impact de la présence d’un testeur dans le même dispositif que le CUT. Les résultats obtenus démontrent que sous certaines limites fréquentielles, le test de balayage à vitesse nominale n’est pas représentatif du mode fonctionnel. Principalement parce que les PIMs présents dans le mode fonctionnel à multiples domaines d’horloge ne sont pas présents dans le mode test, car les horloges multiples ne sont pas distribuées dans ce mode. On conclue également que les PIMs présents dans le mode fonctionnel ont un impact sur les délais de propagation et sur la tension d’alimentation. Finalement, selon nos expérimentations, le testeur, qui génère l’horloge de test, a un impact sur le délai de propagation

Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits

Test power is an important issue in deep submicron semiconductor testing. Too much power supply noise and too much power dissipation can result in excessive temperature rise, both leading to overkill during delay test. Scan-based test has been widely adopted as one of the most commonly used VLSI testing method. The test power during scan testing comprises shift power and capture power. The power consumed in the shift cycle dominates the total power dissipation. It is crucial for IC manufacturing companies to achieve near constant power consumption for a given timing window in order to keep the chip under test (CUT) at a near constant temperature, to make it easy to characterize the circuit behavior and prevent delay test over kill. To achieve constant test power, first, we built a fast and accurate power model, which can estimate the shift power without logic simulation of the circuit. We also proposed an efficient and low power X-bit Filling process, which could potentially reduce both the shift power and capture power. Then, we introduced an efficient test pattern reordering algorithm, which achieves near constant power between groups of patterns. The number of patterns in a group is determined by the thermal constant of the chip. Experimental results show that our proposed power model has very good correlation. Our proposed X-Fill process achieved both minimum shift power and capture power. The algorithm supports multiple scan chains and can achieve constant power within different regions of the chip. The greedy test pattern reordering algorithm can reduce the power variation from 29-126 percent to 8-10 percent or even lower if we reduce the power variance threshold. Excessive noise can significantly affect the timing performance of Deep Sub-Micron (DSM) designs and cause non-trivial additional delay. In delay test generation, test compaction and test fill techniques can produce excessive power supply noise. This can result in delay test overkill. Prior approaches to power supply noise aware delay test compaction are too costly due to many logic simulations, and are limited to static compaction. We proposed a realistic low cost delay test compaction flow that guardbands the delay using a sequence of estimation metrics to keep the circuit under test supply noise more like functional mode. This flow has been implemented in both static compaction and dynamic compaction. We analyzed the relationship between delay and voltage drop, and the relationship between effective weighted switching activity (WSA) and voltage drop. Based on these correlations, we introduce the low cost delay test pattern compaction framework considering power supply noise. Experimental results on ISCAS89 circuits show that our low cost framework is up to ten times faster than the prior high cost framework. Simulation results also verify that the low cost model can correctly guardband every path‟s extra noise-induced delay. We discussed the rules to set different constraints in the levelized framework. The veto process used in the compaction can be also applied to other constraints, such as power and temperature