15,121 research outputs found
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and
is critical in computer systems especially for portable devices with high
performance and more functionality. Clock-gating is the most common technique
used for reducing processor's power. In this work clock gating technique is
applied to optimize the power of fully programmable Embedded Controller (PEC)
employing RISC architecture. The CPU designed supports i) smart instruction
set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies
, iv) RISC as well as controller concepts. The whole design is captured using
VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock
gating technique together is found to reduce the power consumption by 33.33% of
total power consumed by this chip.Comment: 11 pages,11 figures,International Journal Publicatio
Design of an integrated analog controller for a Class-D Audio Amplifier
An integrated analog controller for a self-oscillating class-D audio power amplifier is designed in a 0.35 ÎĽm CMOS technology for a 3.3 Volt power supply. It is intended to be used with an external output stage and passive filter, for medium power applications of upto a few 100 Watts. The controller was optimized with regard to its loop gain to suppress the distortion of the output stage. In typical commercially available output stages, the distortion is dominated by dead time effects and the THD can be as low as 20 dB.
The controller uses self-oscillation to generate the carrier. To control the self-oscillation a second order phase shift network is embedded in the loop. To increase the loop gain a fifth-order loop filter is added. For a switching frequency of 400kHz the controller achieves a loop gain of 51 dB, nearly flat over the audio band. For reasons of flexibility, the order of the controller is made programmable, as well as the dead time and the delay in the loop. Full spice simulations of the controller combined with an external 120 Watt output stage indicate that a THD of upto 80 dB (better than 0.01%) can be obtained even under the worst case condition of a dead time of 50 ns
Efficient Neural Network Implementations on Parallel Embedded Platforms Applied to Real-Time Torque-Vectoring Optimization Using Predictions for Multi-Motor Electric Vehicles
The combination of machine learning and heterogeneous embedded platforms enables new potential for developing sophisticated control concepts which are applicable to the field of vehicle dynamics and ADAS. This interdisciplinary work provides enabler solutions -ultimately implementing fast predictions using neural networks (NNs) on field programmable gate arrays (FPGAs) and graphical processing units (GPUs)- while applying them to a challenging application: Torque Vectoring on a multi-electric-motor vehicle for enhanced vehicle dynamics. The foundation motivating this work is provided by discussing multiple domains of the technological context as well as the constraints related to the automotive field, which contrast with the attractiveness of exploiting the capabilities of new embedded platforms to apply advanced control algorithms for complex control problems. In this particular case we target enhanced vehicle dynamics on a multi-motor electric vehicle benefiting from the greater degrees of freedom and controllability offered by such powertrains. Considering the constraints of the application and the implications of the selected multivariable optimization challenge, we propose a NN to provide batch predictions for real-time optimization. This leads to the major contribution of this work: efficient NN implementations on two intrinsically parallel embedded platforms, a GPU and a FPGA, following an analysis of theoretical and practical implications of their different operating paradigms, in order to efficiently harness their computing potential while gaining insight into their peculiarities. The achieved results exceed the expectations and additionally provide a representative illustration of the strengths and weaknesses of each kind of platform. Consequently, having shown the applicability of the proposed solutions, this work contributes valuable enablers also for further developments following similar fundamental principles.Some of the results presented in this work are related to activities within the 3Ccar project, which has
received funding from ECSEL Joint Undertaking under grant agreement No. 662192. This Joint Undertaking
received support from the European Union’s Horizon 2020 research and innovation programme and Germany,
Austria, Czech Republic, Romania, Belgium, United Kingdom, France, Netherlands, Latvia, Finland, Spain, Italy,
Lithuania. This work was also partly supported by the project ENABLES3, which received funding from ECSEL
Joint Undertaking under grant agreement No. 692455-2
A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units
This paper presents the design and the implementation of a servo-clock (SC)
for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic
Proportional Integral (PI) controller, which has been properly tuned to
minimize the synchronization error due to the local oscillator triggering the
on-board timer. The SC has been implemented into a PMU prototype developed
within the OpenPMU project using a BeagleBone Black (BBB) board. The
distinctive feature of the proposed solution is its ability to track an input
Pulse-Per-Second (PPS) reference with good long-term stability and with no need
for specific on-board synchronization circuitry. Indeed, the SC implementation
relies only on one co-processor for real-time application and requires just an
input PPS signal that could be distributed from a single substation clock
Versatile Data Acquisition and Controls for Epics Using Vme-Based Fpgas
Field-Programmable Gate Arrays (FPGAs) have provided Thomas Jefferson
National Accelerator Facility (Jefferson Lab) with versatile VME-based data
acquisition and control interfaces with minimal development times. FPGA designs
have been used to interface to VME and provide control logic for numerous
systems. The building blocks of these logic designs can be tailored to the
individual needs of each system and provide system operators with read-backs
and controls via a VME interface to an EPICS based computer. This versatility
allows the system developer to choose components and define operating
parameters and options that are not readily available commercially. Jefferson
Lab has begun developing standard FPGA libraries that result in quick turn
around times and inexpensive designs.Comment: 3 pages, ICALEPCS 2001, T. Allison and R. Foold, Jefferson La
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